Abstract: A system and method for a die-to-die interconnect interface and protocol for stacked semiconductor dies. One preferred embodiment comprises an integrated circuit (IC) package comprising a first semiconductor die that includes an interface to a memory-mapped device, a second semiconductor die that does not include an interface to a memory mapped device, and a data bus coupling the first semiconductor die to the second semiconductor die (the data bus used to transfer a control word and a data word). The control word comprises a data word start address that corresponds to a location in the memory-mapped device. The data word is transferred from the second semiconductor die to the first semiconductor die and is stored by the first semiconductor die at the location in the memory-mapped device. Both semiconductor dies are mounted within the IC package.

Abstract: A system and method for a die-to-die interconnect interface and protocol for stacked semiconductor dies. One preferred embodiment comprises an integrated circuit (IC) package comprising a first semiconductor die that includes an interface to a memory-mapped device, a second semiconductor die that does not include an interface to a memory mapped device, and a data bus coupling the first semiconductor die to the second semiconductor die (the data bus used to transfer a control word and a data word). The control word comprises a data word start address that corresponds to a location in the memory-mapped device. The data word is transferred from the second semiconductor die to the first semiconductor die and is stored by the first semiconductor die at the location in the memory-mapped device. Both semiconductor dies are mounted within the IC package.

Abstract: An integrated circuit (“IC”) package comprises a first semiconductor die and a second semiconductor die. The second semiconductor die is coupled to the first semiconductor die within the same IC package. The first semiconductor die includes an interface to memory and the first and second semiconductor dies share said memory. The memory may be located outside or inside the IC package containing the first and second semiconductor dies. In another embodiment, a system comprises a first IC package containing a memory die and a second IC package coupled to the first IC package. The second IC package contains a die stack comprising first and second dies coupled together. The first die includes an interface to the memory die and both of the dies in the die stack share access to the memory die. The system may comprise a communication system such as a cellular telephone.

Abstract: A digital system has a host processor 200 with a bus controller 210 and peripherals 220(0)-220(31) interconnected by an interconnect bus 230. 32 peripherals are share a common strobe line (nSTROBE[0]) on an embodiment of the interconnect bus in a first subdomain. Additional sub-domains, such as sub-domain 260, can be likewise connected to interconnect bus 230. Additional strobe lines nSTROBE(n) are used to select a particular sub-domain in response to an address presented to bus controller 210 by CPU 200. An interconnect bus transaction is synchronized in background so that a current cycle is not delayed. A first write cycle 1500 is completed as a no-wait state transaction, while immediately following second write cycle 1510 is delayed while synchronization circuit 1400 completes the synchronization of the first write cycle. nSTROBE pulse 1520 indicates first write transaction 1500 while nREADY pulse 1530 indicates the completion of a no-wait state first write transaction 1500.

Abstract: A digital system has a host processor 200 with a bus controller 210 and peripherals 220(0)-220(31) interconnected by an interconnect bus 230. 32 peripherals are share a common strobe line (nSTROBE [0]) on an embodiment of the interconnect bus in a first subdomain. Additional sub-domains, such as sub-domain 260, can be likewise connected to interconnect bus 230. Additional strobe lines nSTROBE(n) are used to select a particular sub-domain in response to an address presented to bus controller 210 by CPU 200. A FIFO is provided on a peripheral device to reduce data transfer access time. When the FIFO is almost empty, a FIFO management state machine requests a DMA transfer by asserting the nDMA_REQ signal on the interconnect bus, thus transitioning from idle state 2300 to transfer state 2310 along arc 2301. The DMA controller transfers several data words until the FIFO becomes full, as indicated by word_cpt=FIFO_size.

Abstract: Circuit for multiplying data in accordance with a Booth algorithm, in which the coding of the control signals is adapted to the characteristics of symmetry of a trigonometric function. The values of the function which relate to a single quadrant are stored in a memory and a converter unit makes it possible to utilize the circuit whatever the quadrant. The values of the trigonometric function may be obtained through interpolation. Application to the calculations of Fourier transforms or DCT transforms.