Abstract: A computing system is provided that has a multiprocessor architecture. The processors are hierarchically organized so that one or more slave processors at a senior hierarchical level provide tasks to one or more slave processors at a junior hierarchical level. Further, the slave processors at the junior hierarchical level will have a different functional capability than the slave processors at the senior hierarchical level, such that the junior slave processors can perform some types of operations better than the senior slave processors. A master computing process distributes operation sets among one or more computing processes running on a processor at the senior hierarchical level, which will begin executing operations in the operation set.

Abstract: Layout correction is accomplished using a forward mapping technique. Forward mapping refers to mapping of fragments from a reticle layout to a target layout, while backward mapping refers to mapping of fragments from the target layout to the reticle layout. Forward mapping provides a technique for making an unambiguous mapping for each reticle fragment to a corresponding target layout fragment. The mapping does not necessarily provide a one-to-one correspondence between reticle fragments and target layout fragments. That is, multiple reticle layout fragments can map to a single target layout fragment. An edge placement error for the target layout fragments is used to make positioning corrections for the corresponding reticle fragment(s). Edge placement error can be determined, for example, with a simulation process that simulates a manufacturing process using the reticles.

Abstract: An integrated verification and manufacturability tool provides more efficient verification of integrated device designs than verification using several different verification components. The integrated verification and manufacturability includes a hierarchical database to store shared design data accessed by multiple verification components (e.g., layout versus schematic, design rule check, optical process correction, phase shift mask assignment and OPC verification and machine language conversion). The hierarchical database includes representations of one or more additional, or intermediate layer structures that are created and used by the verification components for operations performed on the design being verified. Use of a single hierarchical database having shared data for access and use by multiple verification components streamlines the verification process, which provides an improved verification tool.

Abstract: A method for performing a matrix-based verification technique such as optical process correction (OPC) that analyzes interactions between movement of a fragment on a mask and one or more edges to be created on a wafer. In one embodiment, each edge to be created is analyzed and one or more fragments of a mask are moved in accordance with a gradient matrix that defines how changes in position of a fragment affect one or more edges on the mask. Fragments are moved having a significant effect on an edge in question. Simulations are performed and fragments are moved in an iterative fashion until each edge has a objective within a prescribed tolerance. In another embodiment, each edge has two or more objectives to be optimized. A objective is selected in accordance with a cost function and fragments are moved in a mask layout until each edge has acceptable specification for each objective.

Abstract: A method of performing a resolution enhancement technique such as OPC on an initial layout description involves fragmenting a polygon that represents a feature to be created into a number of edge fragments. One or more of the edge fragments is assigned an initial simulation site at which the image intensity is calculated. Upon calculation of the image intensity, the position and/or number of initial simulation sites is varied. New calculations are made of the image intensity with the revised placement or number of simulation sites in order to calculate an OPC correction for the edge fragment. In other embodiments, fragmentation of a polygon is adjusted based on the image intensities calculated at the simulation sites. In one embodiment, the image intensity gradient vector calculated at the initial simulation sites is used to adjust the simulation sites and/or fragmentation of the polygon.

Abstract: A method and apparatus for compensating for flare intensity variations across an integrated circuit. A layout description for a physical layer of an integrated circuit or portion thereof is divided into a number of regions such as adjacent tiles. An estimate of the flare intensity in each region is determined. The flare intensity values calculated are divided into a number of ranges. In one embodiment, a data layer in a layout description is defined for each range of flare values computed. Features to be printed in an area having a flare value in a particular range are associated with a corresponding additional data layer. The features associated with each additional data layer are analyzed with a resolution enhancement technique that is selected or adjusted to compensate for differing flare values occurring in the integrated circuit.

Abstract: A method for performing a matrix-based verification technique such as optical process correction (OPC) that analyzes interactions between movement of a fragment on a mask and one or more edges to be created on a wafer. In one embodiment, each edge to be created is analyzed and one or more fragments of a mask are moved in accordance with a gradient matrix that defines how changes in position of a fragment affect one or more edges on the mask. Fragments are moved having a significant effect on an edge in question. Simulations are performed and fragments are moved in an iterative fashion until each edge has a objective within a prescribed tolerance. In another embodiment, each edge has two or more objectives to be optimized. A objective is selected in accordance with a cost function and fragments are moved in a mask layout until each edge has acceptable specification for each objective.

Abstract: An EDA tool is provided with an OPC module that performs optical and/or process pre-compensations on an IC mask layout in a streamlined manner, reusing determined corrections for a first area on a second area, when the second area is determined to be equivalent to the first area for OPC purposes. The OPC module performs the correction on the IC mask layout on an area-by-area basis, and the corrections are determined iteratively using model-based simulations, which in one embodiment, include resist model-based simulations as well as optical model-based simulations.

Abstract: A method for processing objects to be created via photolithography. Each object to be created is defined as a polygon that is fragmented into a number of edge segments that extend around the perimeter of the polygon. At least some of the edge segments have an associated control site where the edge placement error for the edge segment is to be minimal. A smoothing filter is applied to the polygon to identify those control sites that may cause an OPC tool to produce erroneous results. The identified control sites are moved and/or eliminated from the polygon, and polygon and the adjusted control sites are supplied to an OPC tool.

Abstract: A method for performing a matrix-based verification technique such as optical process correction (OPC) that analyzes interactions between movement of a fragment on a mask and one or more edges to be created on a wafer. In one embodiment, each edge to be created is analyzed and one or more fragments of a mask are moved in accordance with a gradient matrix that defines how changes in position of a fragment affect one or more edges on the mask. Fragments are moved having a significant effect on an edge in question. Simulations are performed and fragments are moved in an iterative fashion until each edge has a objective within a prescribed tolerance. In another embodiment, each edge has two or more objectives to be optimized. A objective is selected in accordance with a cost function and fragments are moved in a mask layout until each edge has acceptable specification for each objective.