Patents by Inventor Nicolas Collonville

Nicolas Collonville has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240146242
    Abstract: A free running oscillator in a circuit of an electronic device is calibrated by determining that the circuit of the electronic device is in an awake state; measuring an indication of frequency of the free running oscillator in response to the circuit being in the awake state; and calibrating a frequency of the free running oscillator based on the indication of frequency and the circuit being in the awake state.
    Type: Application
    Filed: May 2, 2023
    Publication date: May 2, 2024
    Inventors: Nicolas Collonville, Axel Le Bourhis
  • Patent number: 11520398
    Abstract: A processor system and method is described. The processor system includes a central processing unit (CPU) comprising a register for storing a stack pointer value, a non-volatile memory coupled to the CPU and having a first non-volatile memory region configured to store instructions executable by the CPU and a second non-volatile memory region configured to store a RAM-image comprising program context data. The processor system includes a random-access memory (RAM) coupled to the CPU and having a first RAM region and a second RAM region. The processor system is configured to have a first operating mode where the RAM data values are not retained and a second operating mode where the RAM is powered on.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: December 6, 2022
    Assignee: NXP USA, Inc.
    Inventor: Nicolas Collonville
  • Publication number: 20210263846
    Abstract: A processor system and method is described. The processor system includes a central processing unit (CPU) comprising a register for storing a stack pointer value, a non-volatile memory coupled to the CPU and having a first non-volatile memory region configured to store instructions executable by the CPU and a second non-volatile memory region configured to store a RAM-image comprising program context data. The processor system includes a random-access memory (RAM) coupled to the CPU and having a first RAM region and a second RAM region. The processor system is configured to have a first operating mode where the RAM data values are not retained and a second operating mode where the RAM is powered on.
    Type: Application
    Filed: February 23, 2021
    Publication date: August 26, 2021
    Inventor: Nicolas Collonville