Abstract: The invention includes a semiconductor device comprising an interlevel dielectric layer over a buried insulator layer over a semiconductor substrate; a source and drain in the interlevel layer; a channel between the source and drain, the channel including a first region having a first bandgap adjacent to a second region having a second bandgap, wherein the first band gap is larger than the second bandgap; and a gate over the channel.

Abstract: A method of making a channel region in a semiconductor device includes providing a substrate having a first transistor area arranged adjacent to a second transistor area; growing an epitaxial layer on the second transistor area of the substrate; forming a trench in the substrate between the first transistor area and the second transistor area; performing a condensation technique to thermally mix materials of the epitaxial layer and the substrate; and filling the trench with a dielectric material to form a shallow trench isolation region between a first channel region of the first transistor and a second channel region of the second transistor; wherein performing the condensation technique is performed after forming the trench.

Abstract: The invention includes a semiconductor device comprising an interlevel dielectric layer over a buried insulator layer over a semiconductor substrate; a source and drain in the interlevel layer; a channel between the source and drain, the channel including a first region having a first bandgap adjacent to a second region having a second bandgap, wherein the first band gap is larger than the second bandgap; and a gate over the channel.

Abstract: The invention includes a semiconductor device comprising an interlevel dielectric layer over a buried insulator layer over a semiconductor substrate; a source and drain in the interlevel layer; a channel between the source and drain, the channel including a first region having a first bandgap adjacent to a second region having a second bandgap, wherein the first band gap is larger than the second bandgap; and a gate over the channel.

Abstract: The invention includes a semiconductor device comprising an interlevel dielectric layer over a buried insulator layer over a semiconductor substrate; a source and drain in the interlevel layer; a channel between the source and drain, the channel including a first region having a first bandgap adjacent to a second region having a second bandgap, wherein the first band gap is larger than the second bandgap; and a gate over the channel.

Abstract: A method of making a channel region in a semiconductor device includes providing a substrate having a first transistor area arranged adjacent to a second transistor area; growing an epitaxial layer on the second transistor area of the substrate; forming a trench in the substrate between the first transistor area and the second transistor area; performing a condensation technique to thermally mix materials of the epitaxial layer and the substrate; and filling the trench with a dielectric material to form a shallow trench isolation region between a first channel region of the first transistor and a second channel region of the second transistor; wherein performing the condensation technique is performed after forming the trench.

Abstract: A method of making a channel region in a semiconductor device includes providing a substrate having a first transistor area arranged adjacent to a second transistor area; growing an epitaxial layer on the second transistor area of the substrate; forming a trench in the substrate between the first transistor area and the second transistor area; performing a condensation technique to thermally mix materials of the epitaxial layer and the substrate; and filling the trench with a dielectric material to form a shallow trench isolation region between a first channel region of the first transistor and a second channel region of the second transistor; wherein performing the condensation technique is performed after forming the trench.

Abstract: A method of making a channel region in a semiconductor device includes providing a substrate having a first transistor area arranged adjacent to a second transistor area; growing an epitaxial layer on the second transistor area of the substrate; forming a trench in the substrate between the first transistor area and the second transistor area; performing a condensation technique to thermally mix materials of the epitaxial layer and the substrate; and filling the trench with a dielectric material to form a shallow trench isolation region between a first channel region of the first transistor and a second channel region of the second transistor; wherein performing the condensation technique is performed after forming the trench.

Abstract: The invention includes a semiconductor device comprising an interlevel dielectric layer over a buried insulator layer over a semiconductor substrate; a source and drain in the interlevel layer; a channel between the source and drain, the channel including a first region having a first bandgap adjacent to a second region having a second bandgap, wherein the first band gap is larger than the second bandgap; and a gate over the channel.

Abstract: The invention includes a semiconductor device comprising an interlevel dielectric layer over a buried insulator layer over a semiconductor substrate; a source and drain in the interlevel layer; a channel between the source and drain, the channel including a first region having a first bandgap adjacent to a second region having a second bandgap, wherein the first band gap is larger than the second bandgap; and a gate over the channel.

Abstract: The invention includes a semiconductor device comprising an interlevel dielectric layer over a buried insulator layer over a semiconductor substrate; a source and drain in the interlevel layer; a channel between the source and drain, the channel including a first region having a first bandgap adjacent to a second region having a second bandgap, wherein the first band gap is larger than the second bandgap; and a gate over the channel.

Abstract: There is provided a method for the manufacture of an integrated circuit, including a substrate and an insulating layer formed on the substrate; a first pMOS transistor formed on the insulating layer and including a channel formed in a first layer of a silicon—germanium alloy, having a first thickness and first average germanium density; a gate oxide layer having a first equivalent oxide thickness; a second pMOS transistor formed on the insulating layer and further including a channel formed in a second layer of a silicon—germanium alloy, having a second thickness which is greater than the first and a second average germanium density which is lower than the first; and a gate oxide layer having a second equivalent oxide thickness which is greater than the first.

Abstract: The invention includes a semiconductor device comprising an interlevel dielectric layer over a buried insulator layer over a semiconductor substrate; a source and drain in the interlevel layer; a channel between the source and drain, the channel including a first region having a first bandgap adjacent to a second region having a second bandgap, wherein the first band gap is larger than the second bandgap; and a gate over the channel.

Abstract: There is provided a method for the manufacture of an integrated circuit, including a substrate and an insulating layer formed on the substrate; a first pMOS transistor formed on the insulating layer and including a channel formed in a first layer of a silicon-germanium alloy, having a first thickness and first average germanium density; a gate oxide layer having a first equivalent oxide thickness; a second pMOS transistor formed on the insulating layer and further including a channel formed in a second layer of a silicon-germanium alloy, having a second thickness which is greater than the first and a second average germanium density which is lower than the first; and a gate oxide layer having a second equivalent oxide thickness which is greater than the first.

Abstract: A method of forming a shallow trench isolation structure such that the shoulders of the wall formations on either side of the trench are rounded, whilst the walls and floor of the trench as well as the top surface of the formations on either side of the trench remain flat. This is achieved by anchoring the walls and floors with a partial gap fill, which may be achieved either by fully filling the gap and then reducing the level to below that of the formations on either side a the trench by polishing and etching steps, or by not completely filling the trench in the first place. The tops of the formations on either side of the trench meanwhile are protected by an oxide layer, which is pared back from the edge of the trench, for example by means of an isotropic etching process.

Abstract: A method for fabricating a shallow trench isolation structure is described, in which a bottom pad oxide layer, a middle silicon nitride layer, a middle oxide layer and a top silicon nitride layer are sequentially formed on a silicon substrate. Photolithographic masking and anisotropic etching are then conducted to form a trench in the substrate. An oxide material is then deposited on top of the top silicon nitride layer, filling up the trenches at the same time. A chemical mechanical polishing step is then employed to remove the oxide material by using the top silicon nitride layer as a barrier layer. The top silicon nitride layer is then removed, followed by an isotropic etch of the oxide layer below. With the middle nitride layer acting as a natural etch stop, the oxide material is sculpted to a desirable shape. The middle nitride layer and the pad oxide layer are subsequently removed to complete the fabrication of a shallow trench isolation structure.

Abstract: A method for fabricating a shallow trench isolation structure is described, in which a bottom pad oxide layer, a middle silicon nitride layer, a middle oxide layer and a top silicon nitride layer are sequentially formed on a silicon substrate. Photolithographic masking and anisotropic etching are then conducted to form a trench in the substrate. An oxide material is then deposited on top of the top silicon nitride layer, filling up the trenches at the same time. A chemical mechanical polishing step is then employed to remove the oxide material by using the top silicon nitride layer as a barrier layer. The top silicon nitride layer is then removed, followed by an isotropic etch of the oxide layer below. With the middle nitride layer acting as a natural etch stop, the oxide material is sculpted to a desirable shape. The middle nitride layer and the pad oxide layer are subsequently removed to complete the fabrication of a shallow trench isolation structure.