Abstract: Power semi-conductor module (1) comprising: —at least one IGBT with a Gate G forming a first electrode (11) and an Emitter E forming a second electrode (12), or —at least one MOSFET with a Gate G forming a first electrode (11) and a Source S forming a second electrode (12). The first electrode (11) includes a polysilicon material made in one piece. The one-piece is made partly of a monitoring portion (13). The monitoring portion (13) is in electrical contact with the second electrode (12) such that a leakage current flows between the first electrode (11) and the second electrode (12) in an operational state of the module (1). The monitoring portion (13) has a location, a form, a size and a material composition selected together such that to have a variable resistance in function of its temperature during the operational state of the module (1).

Abstract: Provided is a method to control a power semiconductor module comprising monitoring at least one operating parameter, and only if the operating parameter is kept into a range and the operating parameter's range has an initial status, initiate a calibration stage. The calibration stage is including measuring a first temperature sensitive electrical parameter, decreasing the dead-time, monitoring said operating parameter, measuring a second temperature sensitive electrical parameter, only if the operating parameter has been kept into said range and the value of the second temperature sensitive electrical parameter corresponds to a lower value of the temperature, assigning the value of the dead-time, else only if the operating parameter has been kept into the range and the value of the second temperature sensitive electrical parameter corresponds to a higher value of the temperature, updating the status, storing the dead-time with the operating parameter's range.

Abstract: The present disclosure relates to a method for estimating parameters of a junction of a power semi-conductor element comprising: •—Detecting at least one stable on-line operating condition through measurements (2, 3, 4) of Von, Ion, Tc on a semi-conductor module (1) where Ion is a current for which the on-state voltage Von of the semi-conductor is sensitive to the temperature and Tc is the temperature of the casing of said semi-conductor element; •—Measuring and storing at least one parameter set Von, Ion, Tc of said at least one stable operating condition; •—in a calculating unit (52), providing calculations for minimizing the error between a junction temperature estimation Tj of an electrical model Tj=F(Von, Ion, ?elec) comprising a first set of unknown parameters ?elec and another junction temperature estimation Tjmod of a loss/thermal model Tj=G(lon, Tc, ? mod) comprising a second set of unknown parameters ? mod and obtaining at least one set of parameters ?elec and at least one parameter ? mod providing

Abstract: A method for estimating degradation of a wire-bonded power semi-conductor module is provided. The method includes obtaining an indicator of degradation (Degrest_t-1); estimating an estimated indicator of degradation (Degrest_t) by a temporal degradation model; obtaining a set of on-line measure (Xon_meas_t); then, (1) converting the on-line measure (Xon_meas_t) into a deducted indicator of degradation (Degrmeas_t) by an electrical equivalence model, and (2) computing a deviation between estimated and deducted indicator of degradation (Degrest_t; Degrmeas_t); and/or (1) converting the estimated indicator of degradation (Degrest_t) into a set of on-line estimation (Xon_est_t), and (2) computing a deviation between set of on-line measure and estimation (Xon_meas_t; Xon_est_t); and correcting the estimated indicator of degradation (Degrest_t) into a corrected estimated indicator of degradation (Degrcorr_t) as a function of the computed deviation.

Abstract: A device having at least one power semiconductor die coated with a metallization and at least one light guide having two opposite ends. The first end is able to be connected at least to a light source and to a light receiver. The second end is permanently fixed facing to a surface of the metallization such that to form a light path towards said surface and a light path from said surface.

Abstract: The present invention concerns a method and device for monitoring the gate signal of a power semiconductor (SI), the gate signal of the power semiconductor (SI) being provided by a gate driver (12), generates an expected signal (VGexp) that corresponds to the signal outputted by the gate driver (12) when no deterioration of the gate driver (12) and/or of the power semiconductor (SI) and/or of a load linked to the power semiconductor (SI) exists, compares the expected signal (VGexp) and the signal (VGmeas) outputted by the gate driver (12), determines if a deterioration of the gate driver (12) and/or of the power semiconductor (SI) and/or of a load linked to the power semiconductor (SI) exists using the result of the comparing of the expected signal (VGexp) and the signal (VGmeas) outputted by the gate driver (12).

Abstract: An inductive assembly includes: a support with an open channel having a straight portion with a bottom surface and two side surfaces, a foldable PCB such that to cover at least a part of the bottom surface and the side surfaces, the PCB having a plurality of tracks, each track being electrically continuous between a pair of connecting spots, a magnetic piece which can be accommodated into the channel equipped with the PCB. The PCB is arranged to surround at least partially a portion of the magnetic piece in the folded state in the channel such that at least one connecting spot of a first track is electrically connected to a connecting spot of a second track to form a winding around the magnetic piece and to inductively couple the PCB and the magnetic piece.

Abstract: A method to establish a degradation state of electrical connections in a power semiconductor device comprising: measuring at least two voltage drop values under two respective current values for the same temperature value. The two current values are strictly different or the measurements are made under two distinct gate levels of a transistor; saving the measured values as calibration data; monitoring operational conditions of said power semiconductor device; measuring at least two voltage drop values under respective same current values as preceding, and at two respective moments during which the monitored operational conditions corresponding to two respective predefined sets of criteria related to states of operation and to a common temperature; saving the at least two values as operational data; calculating a numerical index in a manner to estimate a degradation state of said power semiconductor device.

Abstract: The present invention concerns a device for controlling the switching of a first and a second power semiconductor switches providing current to a load in a half bridge configuration. The device comprises: means for obtaining a first current value through the first switch or the load just before the switching of the first switch from conducting to non-conducting state, means for limiting the current through the second switch during the switching of the second switch from non-conducting to conducting state using the obtained first current value, by modifying the gate signal of the second switch, means for obtaining a second current value through the second switch or the load just before the switching of the second switch from conducting to non-conducting state, means for limiting the current through the first switch during the switching of the first switch from non-conducting to conducting state using the obtained second current value by modifying the gate signal of the first switch.

Abstract: Power semi-conductor module (1) comprising: —at least one IGBT with a Gate G forming a first electrode (11) and an Emitter E forming a second electrode (12), or—at least one MOSFET with a Gate G forming a first electrode (11) and a Source S forming a second electrode (12). The first electrode (11) includes a polysilicon material made in one piece. The one-piece is made partly of a monitoring portion (13). The monitoring portion (13) is in electrical contact with the second electrode (12) such that a leakage current flows between the first electrode (11) and the second electrode (12) in an operational state of the module (1). The monitoring portion (13) has a location, a form, a size and a material composition selected together such that to have a variable resistance in function of its temperature during the operational state of the module (1).

Abstract: A device comprising at least one power semiconductor die coated with a metallization and at least one light guide having two opposite ends. The first end is able to be connected at least to a light source and to a light receiver. The second end is permanently fixed facing to a surface of the metallization such that to form a light path towards said surface and a light path from said surface.

Abstract: The present invention concerns a device for controlling the switching of a first and a second power semiconductor switches providing current to a load in a half bridge configuration. The device comprises: means for obtaining a first current value through the first switch or the load just before the switching of the first switch from conducting to non-conducting state, means for limiting the current through the second switch during the switching of the second switch from non-conducting to conducting state using the obtained first current value, by modifying the gate signal of the second switch, means for obtaining a second current value through the second switch or the load just before the switching of the second switch from conducting to non-conducting state, means for limiting the current through the first switch during the switching of the first switch from non-conducting to conducting state using the obtained second current value by modifying the gate signal of the first switch.

Abstract: Method for estimating degradation of a wire-bonded power semiconductor module (1) comprising: •a) obtaining an indicator of degradation (Degrest_t-1); •b) estimating (11) an estimated indicator of degradation (Degrest_t) by a temporal degradation model; •c) obtaining (3) a set of on-line measure (Xon_meas_t); then, •d1) converting (13) the on-line measure (Xon_meas_t) into a deducted indicator of degradation (Degrmeas_t) by an electrical equivalence model, and •e1) computing (15) a deviation between estimated and deducted indicator of degradation (Degrest_t; Degrmeas_t); and/or •d2) converting (13) the estimated indicator of degradation (Degrest_1) into a set of on-line estimation (Xon_est_t), and •e2) computing (15) a deviation between set of on-line measure and estimation (Xon_ meas_t; Xon_est_t); and •f) correcting (17) the estimated indicator of degradation (Degrest_t) into a corrected estimated indicator of degradation (Degrcorr_t) in function of the computed deviation.

Abstract: The present invention relates to a printed circuit board embedding a power die wherein interconnections between the power die and the printed circuit board are composed of micro/nano wires, the printed circuit board comprising a cavity wherein the power die is placed, and wherein the cavity is further filled with a dielectric fluid.

Abstract: A method estimates a level of damage or a lifetime expectation of a power semiconductor module having at least one die that is mechanically and electrically attached to a ceramic substrate. The ceramic substrate has piezoelectric properties and the method includes: controlling the at least one power die, the control of the at least one power die generating changes in the electrical potential across the ceramic substrate; obtaining information representative of a mechanical deformation of the ceramic substrate; determining if a notification indicating the level of damage or the lifetime expectation has to be performed according to the obtained information and reference information; and notifying the level of damage or the lifetime expectation if the determining step determines that the notification has to be performed.

Abstract: A method to establish a degradation state of electrical connections in a power semiconductor device comprising: measuring at least two voltage drop values under two respective current values for the same temperature value. The two current values are strictly different or the measurements are made under two distinct gate levels of a transistor; saving the measured values as calibration data; monitoring operational conditions of said power semiconductor device; measuring at least two voltage drop values under respective same current values as preceding, and at two respective moments during which the monitored operational conditions corresponding to two respective predefined sets of criteria related to states of operation and to a common temperature; saving the at least two values as operational data; calculating a numerical index in a manner to estimate a degradation state of said power semiconductor device.

Abstract: The present invention concerns a method for estimating a level of damage of an electric device. The method comprises the steps of: forming a histogram of operating cycles related to the electric device for which the level of damage estimation is performed, comparing the formed histogram to histograms of a collection of histograms or to combinations of histograms of the collection of histograms, each histogram of the collection of histogram being associated to a level of damage, in order to determine the histogram of the collection of histograms or the combination of histograms which is the closest from the formed histogram, determining an estimate of the level of damage of the electric device from the level of damage of the closest histogram or from the levels of damages of the histograms of the closest combination of histograms.

Abstract: The present invention concerns a method and a device for estimating a level of damage or a lifetime expectation of a power semiconductor module comprising at least one die that is mechanically, thermally, and electrically attached to a substrate, composed of plural layers of different materials. The invention: obtains power losses of the power semiconductor module, obtains the temperature in at least two different locations of the power semiconductor module, estimates a thermal model between the at least two different locations of the power semiconductor module using the determined power losses and the obtained temperatures, determines if a notification indicating the level of damage or the lifetime expectation has to be performed according to the estimated thermal model and a reference thermal model. notifies the level and location of damage or the lifetime expectation if the determining step determines that the notification has to be performed.

Abstract: The present invention concerns a power module comprising a heat sink, a substrate on which a power die is attached, the power module further comprises between the substrate and the heat sink, a first and a second materials, the first material having a thermal conductivity that is higher than the thermal conductivity of the second material, the second material having a first cavity below the power die and the first material is in the first cavity of the second material.

Abstract: An inductive assembly includes: a support with an open channel having a straight portion with a bottom surface and two side surfaces, a foldable PCB such that to cover at least a part of the bottom surface and the side surfaces, the PCB having a plurality of tracks, each track being electrically continuous between a pair of connecting spots, a magnetic piece which can be accommodated into the channel equipped with the PCB. The PCB is arranged to surround at least partially a portion of the magnetic piece in the folded state in the channel such that at least one connecting spot of a first track is electrically connected to a connecting spot of a second track to form a winding around the magnetic piece and to inductively couple the PCB and the magnetic piece.