Patents by Inventor Nicolas Froidevaux
Nicolas Froidevaux has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11680835Abstract: An oscillating analog signal includes a succession of dampened oscillations. That oscillating analog signal is conditioned to generate an output signal including only oscillations of the oscillating analog signal which have an amplitude smaller than a first threshold. The output signal is then processed by a processing unit, where the first threshold is compatible with a maximum level of voltage tolerable by the processing unit.Type: GrantFiled: January 22, 2021Date of Patent: June 20, 2023Assignee: STMicroelectronics (Rousset) SASInventors: Nicolas Froidevaux, Laurent Lopez
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Patent number: 11509305Abstract: An electronic chip includes a chip core including an input terminal, an output terminal, an external pad, and an input-output circuit coupled to the chip core and the external pad. The input-output circuit includes an enable terminal coupled to the chip core, a connection terminal coupled to the external pad, a switchable diode device coupled between a supply voltage and a reference voltage, and a levelling circuit. The switchable diode device is coupled to the connection terminal and the enable terminal and is configured to operate as a diode in response to a control signal in a first state applied to the enable terminal and to operate as an open circuit in response to the control signal in a second state applied to the enable terminal. The levelling circuit is coupled to the connection terminal, the input terminal of the chip core, and the output terminal of the chip core.Type: GrantFiled: August 25, 2021Date of Patent: November 22, 2022Assignee: STMicroelectronics (Rousset) SASInventors: Nicolas Froidevaux, Laurent Lopez
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Publication number: 20210384903Abstract: An electronic chip includes a chip core including an input terminal, an output terminal, an external pad, and an input-output circuit coupled to the chip core and the external pad. The input-output circuit includes an enable terminal coupled to the chip core, a connection terminal coupled to the external pad, a switchable diode device coupled between a supply voltage and a reference voltage, and a levelling circuit. The switchable diode device is coupled to the connection terminal and the enable terminal and is configured to operate as a diode in response to a control signal in a first state applied to the enable terminal and to operate as an open circuit in response to the control signal in a second state applied to the enable terminal. The levelling circuit is coupled to the connection terminal, the input terminal of the chip core, and the output terminal of the chip core.Type: ApplicationFiled: August 25, 2021Publication date: December 9, 2021Inventors: Nicolas Froidevaux, Laurent Lopez
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Patent number: 11133798Abstract: A device includes a first connection pin, a second connection pin, a third connection pin, and a fourth connection pin. The second connection pin is configured to be connected to a supply voltage. The fourth connection pin is configured to be coupled to a reference voltage. The device further includes a first transistor including: a first gate and a first source/drain coupled to the first connection pin; a second transistor including a second gate and a second source/drain connected to the first transistor; and a third transistor including a third gate, a third source/drain connected to the second transistor, and a fourth source/drain connected to the fourth connection pin. The third transistor is configured to be controlled by a digital signal using the third connection pin. Both the first gate and the second gate are directly connected to the second connection pin.Type: GrantFiled: April 23, 2020Date of Patent: September 28, 2021Assignee: STMICROELECTRONICS (ROUSSET) SASInventors: Nicolas Froidevaux, Laurent Lopez
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Publication number: 20210231478Abstract: An oscillating analog signal includes a succession of dampened oscillations. That oscillating analog signal is conditioned to generate an output signal including only oscillations of the oscillating analog signal which have an amplitude smaller than a first threshold. The output signal is then processed by a processing unit, where the first threshold is compatible with a maximum level of voltage tolerable by the processing unit.Type: ApplicationFiled: January 22, 2021Publication date: July 29, 2021Applicant: STMicroelectronics (Rousset) SASInventors: Nicolas FROIDEVAUX, Laurent LOPEZ
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Publication number: 20200343890Abstract: A device comprising transistors in a series connection is disclosed. In an embodiment a device includes a first transistor, a second transistor connected to the first transistor and a third transistor connected to the second transistor, wherein the transistors are connected in a series connection, and wherein the third transistor is configured to be controlled by a digital signal.Type: ApplicationFiled: April 23, 2020Publication date: October 29, 2020Inventors: Nicolas Froidevaux, Laurent Lopez
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Patent number: 10719331Abstract: A microcontroller includes a core and a unit for managing the power supply of the core that includes an input for receiving an external signal indicating a leaving of a stand-by mode of operation. A signal intercepting unit intercepts the external signal and transmitting it with a delay to the unit for managing.Type: GrantFiled: July 3, 2018Date of Patent: July 21, 2020Assignee: STMicroelectronics (Rousset) SASInventors: Nicolas Froidevaux, Jean-Michel Gril-Maffre, Jean-Pierre Leca
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Patent number: 10502777Abstract: A method of testing a first circuit, including: a) applying a first signal between two terminals of the first circuit, the first circuit being powered off; and b) verifying that radio frequency waves transmitted by the first circuit correspond to an expected transmission.Type: GrantFiled: November 8, 2018Date of Patent: December 10, 2019Assignee: STMICROELECTRONICS (ROUSSET) SASInventors: Yann Bacher, Nicolas Froidevaux
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Publication number: 20190146029Abstract: A method of testing a first circuit, including: a) applying a first signal between two terminals of the first circuit, the first circuit being powered off; and b) verifying that radio frequency waves transmitted by the first circuit correspond to an expected transmission.Type: ApplicationFiled: November 8, 2018Publication date: May 16, 2019Inventors: Yann BACHER, Nicolas FROIDEVAUX
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Patent number: 10217717Abstract: An integrated circuit includes peripheral conductive pads interconnected by a peripheral conductive track within an integrated circuit chip. The integrated circuit chip further includes internal conductive pads interconnected by an internal conductive track within the integrated circuit chip. A conductive bonding wire external to the integrated circuit chip connects the one peripheral conductive pad to one internal conductive pad. A package encapsulates the integrated circuit chip and the conductive bonding wire.Type: GrantFiled: April 25, 2016Date of Patent: February 26, 2019Assignee: STMicroelectronics (Rousset) SASInventors: Nicolas Froidevaux, Yann Bacher
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Publication number: 20180329721Abstract: A microcontroller includes a core and a unit for managing the power supply of the core that includes an input for receiving an external signal indicating a leaving of a stand-by mode of operation. A signal intercepting unit intercepts the external signal and transmitting it with a delay to the unit for managing.Type: ApplicationFiled: July 3, 2018Publication date: November 15, 2018Applicant: STMicroelectronics (Rousset) SASInventors: Nicolas Froidevaux, Jean-Michel Gril-Maffre, Jean-Pierre Leca
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Publication number: 20170147362Abstract: A microcontroller includes a core and a unit for managing the power supply of the core that includes an input for receiving an external signal indicating a leaving of a stand-by mode of operation. A signal intercepting unit intercepts the external signal and transmitting it with a delay to the unit for managing.Type: ApplicationFiled: May 12, 2016Publication date: May 25, 2017Applicant: STMicroelectronics (Rousset) SASInventors: Nicolas Froidevaux, Jean-Michel Gril-Maffre, Jean-Pierre Leca
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Publication number: 20170141069Abstract: An integrated circuit includes peripheral conductive pads interconnected by a peripheral conductive track within an integrated circuit chip. The integrated circuit chip further includes internal conductive pads interconnected by an internal conductive track within the integrated circuit chip. A conductive bonding wire external to the integrated circuit chip connects the one peripheral conductive pad to one internal conductive pad. A package encapsulates the integrated circuit chip and the conductive bonding wire.Type: ApplicationFiled: April 25, 2016Publication date: May 18, 2017Applicant: STMicroelectronics (Rousset) SASInventors: Nicolas Froidevaux, Yann Bacher
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Patent number: 9638728Abstract: A circuit has a supply line, a reference line and circuitry coupled between the supply line and the reference line. The circuitry outputs a regulated voltage and a measurement voltage. An analog-to-digital converter (ADC) generates a digital signal indicative of variations of potential differences between the supply line and the reference line based on the regulated voltage and the measurement voltage. The generated digital signal may be used to control the circuit.Type: GrantFiled: November 20, 2015Date of Patent: May 2, 2017Assignee: STMicroelectronics (Rousset) SASInventors: Yann Bacher, Nicolas Froidevaux
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Publication number: 20160356828Abstract: A circuit has a supply line, a reference line and circuitry coupled between the supply line and the reference line. The circuitry outputs a regulated voltage and a measurement voltage. An analog-to-digital converter (ADC) generates a digital signal indicative of variations of potential differences between the supply line and the reference line based on the regulated voltage and the measurement voltage. The generated digital signal may be used to control the circuit.Type: ApplicationFiled: November 20, 2015Publication date: December 8, 2016Inventors: Yann BACHER, Nicolas FROIDEVAUX
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Patent number: 7843009Abstract: An integrated circuit is made of a semiconductor material and comprises an input and/or terminal connected to an output transistor forming a parasitic element capable of triggering itself under the effect of an electrostatic discharge applied to the terminal. The integrated circuit comprises a protection device formed so as to be biased at the same time as the parasitic element under the effect of an electrostatic discharge, and more than the parasitic element to evacuate a discharge current as a priority.Type: GrantFiled: July 26, 2007Date of Patent: November 30, 2010Assignee: STMicroelectronics SAInventors: John Brunel, Nicolas Froidevaux
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Publication number: 20080048208Abstract: An integrated circuit is made of a semiconductor material and comprises an input and/or output terminal connected to an output transistor forming a parasitic element capable of triggering itself under the effect of an electrostatic discharge applied to the terminal. The integrated circuit comprises a protection device formed so as to be biased at the same time as the parasitic element under the effect of an electrostatic discharge, and more than the parasitic element to evacuate a discharge current as a priority.Type: ApplicationFiled: July 26, 2007Publication date: February 28, 2008Applicant: STMICROELECTRONICS SAInventors: John Brunel, Nicolas Froidevaux
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Patent number: 6807078Abstract: A method produces a semiconductor circuit with an area saving in comparison to conventional circuit layouts. IO cells are arranged with a width multiplied by a factor, but with corresponding reduced height. ESD protection circuitry is included at a reduced rate in comparison to usual arrangements. The space saving is achieved by occupying a semiconductor area that would have been used by ESD circuitry with the IO circuitry. ESD protection is maintained but at different locations.Type: GrantFiled: August 26, 2002Date of Patent: October 19, 2004Assignee: STMicroelectronics LimitedInventors: William Thies, Nicolas Froidevaux
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Publication number: 20030137861Abstract: A method of producing a semiconductor circuit is disclosed with an area saving in comparison to conventional circuit layouts. IO cells are arranged with a width multiplied by a factor, but with corresponding reduced height. ESD protection circuitry is included at a reduced rate in comparison to usual arrangements. The space saving is achieved by occupying a semiconductor area that would have been used by ESD circuitry with the IO circuitry. ESD protection is maintained but at different locations.Type: ApplicationFiled: August 26, 2002Publication date: July 24, 2003Applicant: STMicroelectronics LimitedInventors: William Thies, Nicolas Froidevaux