Patents by Inventor Nicolas Graciannette

Nicolas Graciannette has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CLOSED LOOP END-TO-END QOS ON-CHIP ARCHITECTURE
    Publication number: 20140112149
    Abstract: An apparatus includes an output configured to output data to a communication path of an interconnect for routing to a target and a rate controller configured to control a rate of the output data. The rate controller is configured to control the rate in response to feedback information from the target.
    Type: Application
    Filed: October 21, 2013
    Publication date: April 24, 2014
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Ignazio Antonino Urzi, Nicolas Graciannette, Daniele Mangano
  • VERSATILE DATA PROCESSOR EMBEDDED IN A MEMORY CONTROLLER
    Publication number: 20130061016
    Abstract: A first engine and a memory access controller are each configured to receive memory operation information in parallel. In response to receiving the memory operation information, the first engine is prepared to perform a function on memory data associated with the memory operation and the memory controller is configured to prepare the memory to cause the memory operation to be performed.
    Type: Application
    Filed: September 6, 2012
    Publication date: March 7, 2013
    Applicant: STMicroelectronics, (Grenoble2) SAS
    Inventors: Ignazio Antonino Urzi, Nicolas Graciannette
  • Device and method for synchronizing an exchange of data with a remote member
    Patent number: 7302601
    Abstract: A device is provided for synchronizing, on a reference clock signal, an exchange of data with a remote member. The device includes a main variable delay line controlled by a first processing unit coupled to a phase comparator in order to generate a delayed clock signal transmitted to the remote member. One input of the main variable delay line receives the reference clock signal.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: November 27, 2007
    Assignee: STMicroelectronics S.A.
    Inventors: Nicolas Graciannette, Benoit Marchand
  • Device and method for synchronizing an exchange of data with a remote member
    Publication number: 20030218484
    Abstract: A device is provided for synchronizing, on a reference clock signal, an exchange of data with a remote member. The device includes a main variable delay line controlled by a first processing unit coupled to a phase comparator in order to generate a delayed clock signal transmitted to the remote member. One input of the main variable delay line receives the reference clock signal.
    Type: Application
    Filed: April 2, 2003
    Publication date: November 27, 2003
    Applicant: STMICROELECTRONICS S.A.
    Inventors: Nicolas Graciannette, Benoit Marchand