Abstract: A clock template includes digital programming information for programming clock frames of a programmable gate array (PGA). The digital programming information represents a number of different clock configurations that correspond to various designs in the PGA. In one embodiment, the digital programming information includes a bit stream for partially reconfiguring the PGA. In another embodiment, the digital programming information is embedded in digital programming information of at least one of the designs. Methods of configuring a PGA with different designs having different clocking configurations by utilizing the clock template are also disclosed.

Abstract: A structure and method for operating an asynchronous first in, first out (FIFO) memory system in which the full or empty condition of the memory is determined by comparing a currently-generated write address with a currently-generated read address and a next-to-be-used read address. The current write address and current read address are transmitted from a write address counter and a read address counter, respectively, to a flag control circuit. The flag control circuit includes registers for storing Gray-code versions of the current write address, the current read address, and the next-to-be-used read address, which is determined from the current read address. The flag control circuit generates intermediate ALMOST_EMPTY and ALMOST_FULL signals when the FIFO memory is one data value from being “empty” and “full”, respectively.

Abstract: A comparator circuit for detecting full and empty conditions in a first-in first-out (FIFO) memory system. The comparator circuit includes two-input logic circuits for comparing selected read and write addresses. An almost-empty condition is detected by comparing a next-to-be-used read address value with a currently-used write address value. When these address values are equal, high logic signals are passed by a set of mode control multiplexers to the select terminals of a series of carry chain multiplexers, thereby causing a high logic value to be transmitted to a data input terminal of a first register. The first register latches the high logic signal at the next rising edge of the read clock signal, thereby generating a high EMPTY control signal immediately after a final data value is read from the memory.

Abstract: A system and method for operating an asynchronous first in, first out (FIFO) memory system in which the amount of data stored in a FIFO memory is determined by re-synchronizing a binary read address from a read clock signal to a write clock signal, then subtracting the write-synchronized read address from the binary write address. The FIFO memory system includes the FIFO memory, read and write address counters for generating the binary read address and binary write address, respectively, and a write synchronization circuit. The binary read address is converted into a Gray-code value which is then synchronized to the write clock signal. The write-synchronized Gray-code read address value is then re-converted to binary to form the write-synchronized read address.

Abstract: A first in, first out (FIFO) memory system and method in which the full or empty condition of the FIFO memory is detected before the FIFO memory is actually full or empty, thereby allowing the generation of FULL or EMPTY control signals immediately after a last data value is written into or from the FIFO memory. An almost-empty condition, is detected by comparing the read address and write address values. When the read and write address values indicate that one data value remains in the FIFO memory and a read operation is about to be performed, an ALMOST_EMPTY control signal is applied to a data input terminal of a first register that is clocked by a read clock signal. The ALMOST_EMPTY control signal is latched by the first register at the next rising edge of a read clock signal, thereby causing the register to generate a high EMPTY control signal in the same read clock cycle during which the last data value is read from the FIFO memory.