Patents by Inventor Nicolas J. Moll
Nicolas J. Moll has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7553730Abstract: Synthetic nanopore fabrication methods and structures are provided. Nanoscale transistor fabrication methods and structures are provided.Type: GrantFiled: July 14, 2006Date of Patent: June 30, 2009Assignee: Agilent Technologies, Inc.Inventors: Phillip W. Barth, Thomas Edward Kopley, Nicolas J. Moll, Ying-Lan Chang
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Publication number: 20090142472Abstract: Synthetic nanopore fabrication methods and structures are provided. Nanoscale transistor fabrication methods and structures are provided.Type: ApplicationFiled: July 14, 2006Publication date: June 4, 2009Inventors: Phillip W. Barth, Thomas Edward Kopley, Nicolas J. Moll, Ying-Lan Chang
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Publication number: 20080032238Abstract: Techniques for controlling the size and/or distribution of a catalyst nanoparticles on a substrate are provided. The catalyst nanoparticles comprise any species that can be used for growing a nanostructure, such as a nanotube, on the substrate surface. Polymers are used as a carrier of a catalyst payload, and such polymers self-assemble on a substrate thereby controlling the size and/or distribution of resulting catalyst nanoparticles. Amphiphilic block copolymers are known self-assembly systems, in which chemically-distinct blocks microphase-separate into a nanoscale morphology, such as cylindrical or spherical, depending on the polymer chemistry and molecular weight. Such block copolymers are used as a carrier of a catalyst payload, and their self-assembly into a nanoscale morphology controls size and/or distribution of resulting catalyst nanoparticles onto a substrate.Type: ApplicationFiled: September 16, 2005Publication date: February 7, 2008Inventors: Jennifer Q. Lu, Nicolas J. Moll, Daniel B. Roitman, David T. Dutton
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Patent number: 7087941Abstract: The extraction efficiency of a light emitting device can be improved by making the absorbing device layers as thin as possible. The internal quantum efficiency decreases as the device layers become thinner. An optimal active layer thickness balances both effects. An AlGaInP LED includes a substrate and device layers including an AlGaInP lower confining layer of a first conductivity type, an AlGaInP active region of a second conductivity type, and an AlGaInP upper confining layer of a second conductivity type. The absorbance of the active region is at least one fifth of the total absorbance in the light-emitting device. The device optionally includes at least one set-back layers of AlGaInP interposing one of confining layer and active region. The p-type upper confining layer may be doped with oxygen improve the reliability.Type: GrantFiled: November 5, 2001Date of Patent: August 8, 2006Assignee: Philips Lumileds Lighting Company, LLCInventors: Nathan F. Gardner, Fred A. Kish, Herman C. Chui, Stephen A. Stockman, Michael R. Krames, Gloria E. Hofler, Christopher Kocot, Nicolas J. Moll, Tun-Sein Tan
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Patent number: 7052618Abstract: Nanostructures and methods of making the same are described. In one aspect, a film including a vector polymer comprising a payload moiety is formed on a substrate. The film is patterned. Organic components of the patterned film are removed to form a payload-comprising nanoparticle.Type: GrantFiled: January 28, 2004Date of Patent: May 30, 2006Assignee: Agilent Technologies, Inc.Inventors: Nicolas J. Moll, Daniel B. Roitman, Jennifer Q. Lu
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Patent number: 6992337Abstract: A heterojunction bipolar transistor (HBT), comprises a collector formed over a substrate, a base formed over the collector, an emitter formed over the base, and a tunneling suppression layer between the collector and the base, the tunneling suppression layer fabricated from a material that is different from a material of the base and that has an electron affinity equal to or greater than an electron affinity of the material of the base.Type: GrantFiled: April 2, 2004Date of Patent: January 31, 2006Assignee: Agilent Technologies, Inc.Inventors: Sandeep Bahl, Nicolas J. Moll
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Patent number: 6949008Abstract: A method for planarizing a substrate surface having a non-planar surface topography comprises forming a material layer over the substrate, the material layer having a surface topography, determining the surface topography of the material layer, and forming a mask using information relating to the surface topography of the material layer. The mask defines portions of averaging regions of the material layer for selective removal to equalize the averaging regions in average height, the averaging regions having a maximum dimension. The material layer is etched using the mask, and a planarizing layer is formed over the substrate surface. The planarizing layer provides a low-pass lateral filtering effect characterized by a length greater than the maximum dimension of the averaging region.Type: GrantFiled: October 19, 2004Date of Patent: September 27, 2005Assignee: Agilent Technologies, Inc.Inventors: Nicolas J. Moll, John Stephen Kofol, David Thomas Dutton
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Patent number: 6822274Abstract: A heterojunction for a semiconductor device. The heterojunction has a first region formed from a first semiconductor material having a first conductivity type, a second region formed from a second semiconductor material having a second conductivity type, and an intermediate layer between the first region and the second region. The band line-up of the first region, the intermediate layer, and the second region has no bound states in its conduction band and no bound states in its valence band. The intermediate layer has a thickness small enough to allow electrons to tunnel from the first region to the second region with negligible attenuation. The semiconductor device may be a heterojunction bipolar transistor. The conduction band of the intermediate layer has a higher energy level than the conduction bands of the first and second regions.Type: GrantFiled: February 3, 2003Date of Patent: November 23, 2004Assignee: Agilent Technologies, Inc.Inventors: Sung Soo Yi, Nicolas J. Moll, Dave Bour, Hans G. Rohdin
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Publication number: 20040149994Abstract: A heterojunction for a semiconductor device. The heterojunction has a first region formed from a first semiconductor material having a first conductivity type, a second region formed from a second semiconductor material having a second conductivity type, and an intermediate layer between the first region and the second region. The band line-up of the first region, the intermediate layer, and the second region has no bound states in its conduction band and no bound states in its valence band. The intermediate layer has a thickness small enough to allow electrons to tunnel from the first region to the second region with negligible attenuation. The semiconductor device may be a heterojunction bipolar transistor. The conduction band of the intermediate layer has a higher energy level than the conduction bands of the first and second regions.Type: ApplicationFiled: February 3, 2003Publication date: August 5, 2004Inventors: Sung Soo Yi, Nicolas J. Moll, Dave Bour, Hans G. Rohdin
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Patent number: 6768141Abstract: A heterojunction bipolar transistor (HBT), including an emitter formed from a first semiconductor material, a base formed from a second semiconductor material, and a grading structure between the emitter and the base is disclosed. The grading structure comprises a semiconductor material containing at least one element not present in the first and second semiconductor materials, where the grading structure has a conduction band energy substantially equal to a conduction band energy of the base at an interface between the base and the grading structure, and where the grading structure has a conduction band energy substantially equal to a conduction band energy of the emitter at an interface between the emitter and the grading structure.Type: GrantFiled: August 23, 2002Date of Patent: July 27, 2004Assignee: Agilent Technologies, Inc.Inventors: Sandeep R. Bahl, Nicolas J. Moll, Mark Hueschen
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Patent number: 6762480Abstract: An HBT having an InP collector, a GaAsSb base and an InP emitter in which the base is constructed using a thin layer of GaAsSb. The thin base layer can be constructed of a GaAsSb material with a composition having a bulk lattice constant that matches the bulk lattice constant of the material of the collector. The thickness of the GaAsSb base layer is less than 49 nm, and preferably less that about 20 nm. Alternatively, the thin base layer is of a GaAsSb composition that includes a higher As content, resulting in a low conduction band energy discontinuity at the emitter-base junction. Such a GaAsSb base layer has a lattice constant that conforms to the lattice constant of the collector because it is thinly grown so as to be pseudomorphically “strained” over the collector. A high base doping level is used to reduce the sheet resistivity and lower the base series resistance that results from the thinly grown base layer.Type: GrantFiled: February 27, 2001Date of Patent: July 13, 2004Assignee: Agilent Technologies, Inc.Inventors: Nicolas J. Moll, Colombo R. Bolognesi
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Publication number: 20040104403Abstract: An HBT having an InP collector, a GaAsSb base and an InP emitter in which the base is constructed using a thin layer of GaAsSb. The thin base layer can be constructed of a GaAsSb material with a composition having a bulk lattice constant that matches the bulk lattice constant of the material of the collector. The thickness of the GaAsSb base layer is less than 49 nm, and preferably less that about 20 nm. Alternatively, the thin base layer is of a GaAsSb composition that includes a higher As content, resulting in a low conduction band energy discontinuity at the emitter-base junction. Such a GaAsSb base layer has a lattice constant that conforms to the lattice constant of the collector because it is thinly grown so as to be pseudomorphically “strained” over the collector. A high base doping level is used to reduce the sheet resistivity and lower the base series resistance that results from the thinly grown base layer.Type: ApplicationFiled: November 12, 2003Publication date: June 3, 2004Inventors: Nicolas J. Moll, Colombo R. Bolognesi
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Publication number: 20040036082Abstract: A heterojunction bipolar transistor (HBT), including an emitter formed from a first semiconductor material, a base formed from a second semiconductor material, and a grading structure between the emitter and the base is disclosed. The grading structure comprises a semiconductor material containing at least one element not present in the first and second semiconductor materials, where the grading structure has a conduction band energy substantially equal to a conduction band energy of the base at an interface between the base and the grading structure, and where the grading structure has a conduction band energy substantially equal to a conduction band energy of the emitter at an interface between the emitter and the grading structure.Type: ApplicationFiled: August 23, 2002Publication date: February 26, 2004Inventors: Sandeep R. Bahl, Nicolas J. Moll, Mark Hueschen
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Patent number: 6696710Abstract: A heterojunction bipolar transistor (HBT) having a base-emitter junction that exhibits the desirable properties of a GaAsSb/AlInAs interface, but which includes an intermediate layer in the emitter such that the intermediate layer contacts the GaAsSb base and the AlInAs emitter. The intermediate layer is sufficiently thin to be substantially electrically transparent, but sufficiently thick to provide a surface over which to grow the AlInAs emitter. The intermediate layer may be of a material such as InP, which has a bulk lattice constant that matches the lattice constant of the GaAsSb base and the AlInAs emitter. Alternatively, the intermediate layer may be of a material having a lattice constant different than that of the GaAsSb base and the AlInAs emitter, but may be pseudomorphically grown so as to provide an apparent lattice-match to the GaAsSb base and the AlInAs emitter.Type: GrantFiled: February 27, 2001Date of Patent: February 24, 2004Assignee: Agilent Technologies, Inc.Inventors: Nicolas J. Moll, Yu-Min Houng
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Publication number: 20020145137Abstract: An HBT having an InP collector, a GaAsSb base and an InP emitter in which the base is constructed using a thin layer of GaAsSb. The thin base layer can be constructed of a GaAsSb material with a composition having a bulk lattice constant that matches the bulk lattice constant of the material of the collector. The thickness of the GaAsSb base layer is less than 49 nm, and preferably less that about 20 nm. Alternatively, the thin base layer is of a GaAsSb composition that includes a higher As content, resulting in a low conduction band energy discontinuity at the emitter-base junction. Such a GaAsSb base layer has a lattice constant that conforms to the lattice constant of the collector because it is thinly grown so as to be pseudomorphically “strained” over the collector. A high base doping level is used to reduce the sheet resistivity and lower the base series resistance that results from the thinly grown base layer.Type: ApplicationFiled: February 27, 2001Publication date: October 10, 2002Inventors: Nicolas J. Moll, Colombo R. Bolognesi
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Publication number: 20020127751Abstract: The extraction efficiency of a light emitting device can be improved by making the absorbing device layers as thin as possible. The internal quantum efficiency decreases as the device layers become thinner. An optimal active layer thickness balances both effects. An AlGaInP LED includes a substrate and device layers including an AlGaInP lower confining layer of a first conductivity type, an AlGaInP active region of a second conductivity type, and an AlGaInP upper confining layer of a second conductivity type. The absorbance of the active region is at least one fifth of the total absorbance in the light-emitting device. The device optionally includes at least one set-back layers of AlGaInP interposing one of confining layer and active region. The p-type upper confining layer may be doped with oxygen improve the reliability.Type: ApplicationFiled: November 5, 2001Publication date: September 12, 2002Inventors: Nathan F. Gardner, Fred A. Kish, Herman C. Chui, Stephen A. Stockman, Michael R. Krames, Gloria E. Hofler, Christopher Kocot, Nicolas J. Moll, Tun-Sein Tan
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Publication number: 20020117657Abstract: A heterojunction bipolar transistor (BBT) having a base-emitter junction that exhibits the desirable properties of a GaAsSb/AlInAs interface, but which includes an intermediate layer in the emitter such that the intermediate layer contacts the GaAsSb base and the AlInAs emitter. The intermediate layer is sufficiently thin to be substantially electrically transparent, but sufficiently thick to provide a surface over which to grow the AlInAs emitter. The intermediate layer may be of a material such as InP, which has a bulk lattice constant that matches the lattice constant of the GaAsSb base and the AlInAs emitter. Alternatively, the intermediate layer may be of a material having a lattice constant different than that of the GaAsSb base and the AlInAs emitter, but may be pseudomorphically grown so as to provide an apparent lattice-match to the GaAsSb base and the AlInAs emitter.Type: ApplicationFiled: February 27, 2001Publication date: August 29, 2002Inventors: Nicolas J. Moll, Yu-Min Houng
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Publication number: 20010020703Abstract: The extraction efficiency of a light emitting device can be improved by making the absorbing device layers as thin as possible. The internal quantum efficiency decreases as the device layers become thinner. An optimal active layer thickness balances both effects. An AlGaInP LED includes a substrate and device layers including an AlGaInP lower confining layer of a first conductivity type, an AlGaInP active region of a second conductivity type, and an AlGaInP upper confining layer of a second conductivity type. The absorbance of the active region is at least one fifth of the total absorbance in the light-emitting device. The device optionally includes at least one set-back layers of AlGaInP interposing one of confining layer and active region. The p-type upper confining layer may be doped with oxygen improve the reliability.Type: ApplicationFiled: July 24, 1998Publication date: September 13, 2001Inventors: NATHAN F. GARDNER, FRED A. KISH, HERMAN C. CHUI, STEPHEN A. STOCKMAN, MICHAEL R. KRAMES, GLORIA E. HOFLER, CHRISTOPHER KOCOT, NICOLAS J. MOLL
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Patent number: 6258639Abstract: A transistor structure with a degradation-stop layer that prevents degradation of underlying semiconductor layers while minimizing any increase in the gate leakage current is disclosed. In one embodiment, a transistor structure includes: a substrate; a channel layer formed of a charge transport material over the substrate; a Schottky barrier layer formed of an aluminum-containing material over the channel layer; a degradation-stop layer formed of a substantially aluminum-free material over the Schottky barrier layer; and a source, a drain and a gate. The source and the drain being formed over or alloyed through the degradation-stop layer, and a lower portion of the gate extends down through an exposed portion of the degradation-stop layer and is in physical and electrical contact with the Schottky barrier layer.Type: GrantFiled: May 21, 1999Date of Patent: July 10, 2001Assignee: Agilent Technologies, Inc.Inventors: Hans Rohdin, Chung-Yi Su, Arlene Sachiyo Wakita-Oyama, Nicolas J. Moll
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Patent number: 5497012Abstract: A semiconductor diode for providing a reduced recovery time at room temperature independent of any minority carrier recombination. The diode of the present invention comprises a first semiconductor material having a type of majority carriers and having a sub-band ordering associated with the majority carriers. The diode further comprises a second semiconductor material contacting the first material at a heterojunction, the second semiconductor material having the same type of majority carriers as the first semiconductor material and having a sub-band ordering associated with the majority carriers that is different from that of the first semiconductor material. It is theorized that the semiconductor diode of the present invention has a recovery time dependent upon scattering of carriers to various energy sub-bands within a heterojunction of the two different semiconductor materials. The diode of the present invention provides a reduced recovery time since a time of such scattering is extremely short.Type: GrantFiled: June 15, 1994Date of Patent: March 5, 1996Assignee: Hewlett-Packard CompanyInventor: Nicolas J. Moll