Abstract: Contact openings are formed into a dielectric material exposing a surface portion of a semiconductor substrate. An interfacial oxide layer is then formed in each contact opening and on an exposed surface portion of the interfacial oxide layer. A NiPt alloy layer is formed within each opening and on the exposed surface portion of each interfacial oxide layer. An anneal is then performed that forms a contact structure of, from bottom to top, a nickel disilicide alloy body having an inverted pyramidal shape, a Pt rich silicide cap region and an oxygen rich region. A metal contact is then formed within each contact opening and atop the oxygen rich region of each contact structure.

Abstract: A contact is created by forming a layer of dielectric material on a silicon-containing region of a semiconductor substrate. An opening is created through the layer of dielectric material, the opening having a bottom and exposing the silicon-containing region. An oxygen-containing layer is formed on type of the semiconductor substrate. A metal stack is formed within the opening and includes a first metal film with a first type of metal and a second type of metal and a second metal film. The metal stack, the oxygen-containing layer and the silicon-containing region of the semiconductor substrate are annealed to form a metallic oxide layer and a metal silicide layer. A first liner is formed within the opening. A fill metal is deposited in the opening.

Abstract: A method of forming a stable nickel silicide layer is provided. The method may include forming a nickel silicide layer on a substrate. A fluorine-rich nickel layer is formed over the nickel silicide layer. The fluorine-rich nickel layer is subjected to a process that drives the fluorine in the fluorine-rich nickel layer into the nickel silicide layer thereunder.

Abstract: A deep trench capacitor is provided. The deep trench capacitor may include: a deep trench in a substrate, the deep trench including an lower portion having a width that is wider than a width of the rest of the deep trench; a compressive stress layer against the substrate in the lower portion; a metal-insulator-metal (MIM) stack over the compressive stress layer, the MIM stack including a node dielectric between an inner electrode and an outer electrode; and a semiconductor core within the MIM stack.

Abstract: Method of forming a deep trench capacitor are provided. The method may include forming a deep trench in a substrate; forming a metal-insulator-metal (MIM) stack within a portion of the deep trench, the MIM stack forming including forming an outer electrode by co-depositing a refractory metal and silicon into the deep trench; and filling a remaining portion of the deep trench with a semiconductor.

Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating more particularly to a structure and method for fabricating silicides with different compositions and/or thicknesses on a single structure having more than one type of device using laser annealing. A method is disclosed that includes using a photoresist compatible with a laser annealing process to protect a region of a semiconductor substrate from silicide formation.

Abstract: A gate structure is provided on a channel portion of a semiconductor substrate. The gate structure may include an electrically conducting layer present on a gate dielectric layer, a semiconductor-containing layer present on the electrically conducting layer, a metal semiconductor alloy layer present on the semiconductor-containing layer, and a dielectric capping layer overlaying the metal semiconductor alloy layer. In some embodiments, carbon and/or nitrogen can be present within the semiconductor-containing layer, the metal semiconductor alloy layer or both the semiconductor-containing layer and the metal semiconductor alloy layer. The presence of carbon and/or nitrogen within the semiconductor-containing layer and/or the metal semiconductor alloy layer provides stability to the gate structure. In another embodiment, a layer of carbon and/or nitrogen can be formed between the semiconductor-containing layer and the metal semiconductor alloy layer.

Abstract: Method of forming a deep trench capacitor are provided. The method may include forming a deep trench in a substrate; enlarging a width of a lower portion of the deep trench to be wider than a width of the rest of the deep trench; epitaxially forming a compressive stress layer in the lower portion of the deep trench; forming a metal-insulator-metal (MIM) stack within the lower portion of the deep trench; and filling a remaining portion of the deep trench with a semiconductor. Alternatively to forming the compressive stress layer or in addition thereto, a silicide may be formed by co-deposition of a refractory metal and silicon.

Abstract: A contact can be formed by forming a layer of dielectric material on a silicon-containing region of a semiconductor substrate. An opening is created through the layer of dielectric material that exposes the silicon-containing region. A metal stack is formed within the opening. The metal stack includes at least a first metal film having a first and second type of metal and a second metal film. The metal stack and the silicon-containing region of the semiconductor substrate are annealed to form a silicide that includes the first and second types of metal and that is in contact with the semiconductor substrate. A first liner is formed within the opening and a fill metal is deposited in the opening.

Abstract: Contact openings are formed into a dielectric material exposing a surface portion of a semiconductor substrate. An interfacial oxide layer is then formed in each contact opening and on an exposed surface portion of the interfacial oxide layer. A NiPt alloy layer is formed within each opening and on the exposed surface portion of each interfacial oxide layer. An anneal is then performed that forms a contact structure of, from bottom to top, a nickel disilicide alloy body having an inverted pyramidal shape, a Pt rich silicide cap region and an oxygen rich region. A metal contact is then formed within each contact opening and atop the oxygen rich region of each contact structure.

Abstract: A contact is created by forming a layer of dielectric material on a silicon-containing region of a semiconductor substrate. An opening is created through the layer of dielectric material, the opening having a bottom and exposing the silicon-containing region. An oxygen-containing layer is formed on type of the semiconductor substrate. A metal stack is formed within the opening and includes a first metal film with a first type of metal and a second type of metal and a second metal film. The metal stack, the oxygen-containing layer and the silicon-containing region of the semiconductor substrate are annealed to form a metallic oxide layer and a metal silicide layer. A first liner is formed within the opening. A fill metal is deposited in the opening.

Abstract: Semiconductor chips with curable out of specification measured values of an anneal-activated parameter are identified at a test step. A plurality of anneal plans are generated to include at least one of the identified semiconductor chips. A net yield improvement is calculated for each anneal plan. Each anneal plan includes the paths of a laser beam across the wafer to be irradiated, and optionally includes an azimuthal angle of the wafer as a function of time. The net yield improvement is the difference between an estimated yield improvement from selected target semiconductor chips for irradiation and an estimated yield loss due to collateral irradiation of functional semiconductor chips for each anneal plan. After simulating the net yield improvements for all the anneal plans, the anneal plan providing the greatest net yield improvement can be selected and utilized.

Abstract: Contact openings are formed into a dielectric material exposing a surface portion of a semiconductor substrate. A first transition metal liner including at least one first transition metal element, a second transition metal liner including at least one second transition metal element that is different from the at least one first transition metal element and a metal contact are sequentially formed within each contact opening. Following a planarization process, the structure is annealed forming metal semiconductor alloy contacts at the bottom of each contact opening. Each metal semiconductor alloy contact that is formed includes the at least one first transition metal element, the at least one second transition metal element and a semiconductor element.

Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating more particularly to a structure and method for fabricating silicides with different compositions and/or thicknesses on a single structure having more than one type of device using laser annealing. A method is disclosed that includes using a photoresist compatible with a laser annealing process to protect a region of a semiconductor substrate from silicide formation.

Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating more particularly to a structure and method for fabricating silicides with different compositions and/or thicknesses on a single structure having more than one type of device using laser annealing. A method is disclosed that includes using a photoresist compatible with a laser annealing process to protect a region of a semiconductor substrate from silicide formation.

Abstract: A gate structure is provided on a channel portion of a semiconductor substrate. The gate structure may include an electrically conducting layer present on a gate dielectric layer, a semiconductor-containing layer present on the electrically conducting layer, a metal semiconductor alloy layer present on the semiconductor-containing layer, and a dielectric capping layer overlaying the metal semiconductor alloy layer. In some embodiments, carbon and/or nitrogen can be present within the semiconductor-containing layer, the metal semiconductor alloy layer or both the semiconductor-containing layer and the metal semiconductor alloy layer. The presence of carbon and/or nitrogen within the semiconductor-containing layer and/or the metal semiconductor alloy layer provides stability to the gate structure. In another embodiment, a layer of carbon and/or nitrogen can be formed between the semiconductor-containing layer and the metal semiconductor alloy layer.

Abstract: A gate structure is provided on a channel portion of a semiconductor substrate. The gate structure may include an electrically conducting layer present on a gate dielectric layer, a semiconductor-containing layer present on the electrically conducting layer, a metal semiconductor alloy layer present on the semiconductor-containing layer, and a dielectric capping layer overlaying the metal semiconductor alloy layer. In some embodiments, carbon and/or nitrogen can be present within the semiconductor-containing layer, the metal semiconductor alloy layer or both the semiconductor-containing layer and the metal semiconductor alloy layer. The presence of carbon and/or nitrogen within the semiconductor-containing layer and/or the metal semiconductor alloy layer provides stability to the gate structure. In another embodiment, a layer of carbon and/or nitrogen can be formed between the semiconductor-containing layer and the metal semiconductor alloy layer.

Abstract: A gate structure is provided on a channel portion of a semiconductor substrate. The gate structure may include an electrically conducting layer present on a gate dielectric layer, a semiconductor-containing layer present on the electrically conducting layer, a metal semiconductor alloy layer present on the semiconductor-containing layer, and a dielectric capping layer overlaying the metal semiconductor alloy layer. In some embodiments, carbon and/or nitrogen can be present within the semiconductor-containing layer, the metal semiconductor alloy layer or both the semiconductor-containing layer and the metal semiconductor alloy layer. The presence of carbon and/or nitrogen within the semiconductor-containing layer and/or the metal semiconductor alloy layer provides stability to the gate structure. In another embodiment, a layer of carbon and/or nitrogen can be formed between the semiconductor-containing layer and the metal semiconductor alloy layer.