Patents by Inventor Nicolas L'Hostis

Nicolas L'Hostis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250134185
    Abstract: Embodiments of the present the disclosure relate to apparatuses, systems (100), and methods for flexible electronic panels (102) that can be incorporated into various garments (104). In an exemplary embodiment the electronic panel (102) comprises a substrate (118) and an electrically conductive wire (120) attached to the substrate (118). Exemplary embodiments include a garment (104) comprising a plurality of panels (102,A?,A?,A??,Bl,B?). In aspects, a first panel (102) is a unitary panel extending from a first appendage of the garment (104) to a second appendage of the garment (104). Additionally, at least the first panel (102) comprises at least one conductive wire (120) and wherein the remaining plurality of panels (A?,A?,A??,BI,B?) form the remainder of the garment (104).
    Type: Application
    Filed: February 2, 2023
    Publication date: May 1, 2025
    Inventors: Clemens Deilmann, Joachim Kuhnke, Joachim Mueller, Nicolas L. Poirette-Lanteaume
  • Publication number: 20250057647
    Abstract: The present invention relates to the production of a valve leaflet implant and to the use thereof in the treatment of congenital heart disease, cardiac, venous and lymphatic valvulopathies, in particular the tetralogy of Fallot.
    Type: Application
    Filed: December 21, 2022
    Publication date: February 20, 2025
    Inventors: Fabien KAWECKI, Nicolas L’HEUREUX, Jean-Benoît THAMBO, François ROUBERTIE
  • Patent number: 12154623
    Abstract: Techniques for controlling current through memory cells is disclosed. In the illustrative embodiment, a fine-grained current source and a coarse-grained current source can both be activated to perform an operation on a phase-change memory cell. The coarse-grained current source is briefly activated to charge up the capacitance of an electrical path through the memory cell and then turned off. The fine-grained current source applies a current pulse to perform the operation on the memory cell, such as a reset operation. By charging up the electrical path quickly with the coarse-grained current source, the fine-grained current source can quickly perform the operation on the memory cell, reducing the thermal disturbance caused by the operation on nearby memory cells.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: November 26, 2024
    Assignee: Intel Corporation
    Inventors: Noble Narku-Tetteh, Yasir Mohsin Husain, Ripudaman Singh, Nicolas L. Irizarry
  • Patent number: 12062410
    Abstract: A method, apparatus and system. The method includes: generating a feedback voltage VFB in a feedback circuit coupled to one of a bitline node (BL) or a wordline node (WL) of each of a plurality of memory cells of a memory array, the feedback voltage to, in a thresholded state of said each of the memory cells, counteract a decrease in an absolute value of a voltage Vvdm at said one of the BL or WL; generating, in a reference circuit, one of a reference voltage VREF to track a feedback voltage of the feedback circuit or a mirror current IMFBmirror to track a current Icell through said each of the memory cells; and providing one of values for both VFB and VREF, or for an output voltage Vapsout corresponding to IMFBmirror, to a sense circuitry, the sense circuitry to determine a logic state of said each of the memory cells based on a comparison of VFB with VREF or based on Vapsout.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: August 13, 2024
    Assignee: Intel Corporation
    Inventors: Ashraf B. Islam, Jaydip Bharatkumar Patel, Yasir Mohsin Husain, Balaji Srinivasan, Nicolas L. Irizarry
  • Publication number: 20220371211
    Abstract: Anti-clogging manual razor cartridge equipped with an arrangement of rollers and cutting blades arranged in an alternating manner with each other, namely, a leading roller, a leading cutting blade, a trailing roller, a trailing cutting blade and a final cutting blade. Each of the cutting blades are bent to obliquely angle two portions thereof with one of the two portions terminating into a sharpened edge. The arrangement is such that the sharpened edge of the leading cutting blade is over the leading roller, the sharpened edge of the trailing cutting blade is over the trailing roller, the sharpened edge of the final cutting blade is over the trailing cutting blade.
    Type: Application
    Filed: August 8, 2022
    Publication date: November 24, 2022
    Inventors: Erin K. Seferi, Nicolas L. Seferi
  • Publication number: 20220270680
    Abstract: Techniques for controlling current through memory cells is disclosed. In the illustrative embodiment, a fine-grained current source and a coarse-grained current source can both be activated to perform an operation on a phase-change memory cell. The coarse-grained current source is briefly activated to charge up the capacitance of an electrical path through the memory cell and then turned off. The fine-grained current source applies a current pulse to perform the operation on the memory cell, such as a reset operation. By charging up the electrical path quickly with the coarse-grained current source, the fine-grained current source can quickly perform the operation on the memory cell, reducing the thermal disturbance caused by the operation on nearby memory cells.
    Type: Application
    Filed: February 24, 2021
    Publication date: August 25, 2022
    Applicant: Intel Corporation
    Inventors: Noble Narku-Tetteh, Yasir Mohsin Husain, Ripudaman Singh, Nicolas L. Irizarry
  • Publication number: 20220180905
    Abstract: A method, apparatus and system. The method includes: generating a feedback voltage VFB in a feedback circuit coupled to one of a bitline node (BL) or a wordline node (WL) of each of a plurality of memory cells of a memory array, the feedback voltage to, in a thresholded state of said each of the memory cells, counteract a decrease in an absolute value of a voltage Vvdm at said one of the BL or WL; generating, in a reference circuit, one of a reference voltage VREF to track a feedback voltage of the feedback circuit or a mirror current IMFBmirror to track a current Icell through said each of the memory cells; and providing one of values for both VFB and VREF, or for an output voltage Vapsout corresponding to IMFBmirror, to a sense circuitry, the sense circuitry to determine a logic state of said each of the memory cells based on a comparison of VFB with VREF or based on Vapsout.
    Type: Application
    Filed: December 7, 2020
    Publication date: June 9, 2022
    Applicant: Intel Corporation
    Inventors: Ashraf B. Islam, Jaydip Bharatkumar Patel, Yasir Mohsin Husain, Balaji Srinivasan, Nicolas L. Irizarry
  • Patent number: 11088280
    Abstract: The disclosure provides for a transistor which may include: a gate stack on a substrate, the gate stack including a gate dielectric and a gate electrode over the gate dielectric; a channel within the substrate and under the gate stack; a doped source and a doped drain on opposing sides of the channel, the doped source and the doped drain each including a dopant, wherein the dopant and the channel together have a first coefficient of diffusion and the doped source and the doped drain each have a second coefficient of diffusion; and a doped extension layer separating each of the doped source and the doped drain from the channel, the doped extension layer having a third coefficient of diffusion, wherein the third coefficient of diffusion is greater than the first coefficient of diffusion and the second coefficient of diffusion is less than the third coefficient of diffusion.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: August 10, 2021
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Nicolas L. Breil, Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 11069809
    Abstract: Fabrication method for a semiconductor device and structure are provided, which includes: providing an isolation layer at least partially disposed adjacent to at least one sidewall of a fin structure extended above a substrate structure, the fin structure including a channel region; recessing an exposed portion of the fin structure to define a residual stress to be induced into the channel region of the fin structure, wherein upper surfaces of a recessed fin portion and the isolation layer are coplanar with each other; and epitaxially growing a semiconductor material from the recessed exposed portion of the fin structure to form at least one of a source region and a drain region of the semiconductor device.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: July 20, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Alexander Reznicek, Shogo Mochizuki, Veeraraghavan S. Basker, Nicolas L. Breil, Oleg Gluschenkov
  • Patent number: 10922809
    Abstract: A method for detecting voids in a metal line of a semiconductor device die includes: scanning an electron beam upon a selected location on the die containing the metal line; determine gray levels in an image produced by collected electrons of the electron beam backscattered from the selected location on the die; and identifying one or more voids in the metal line based on differences between the gray levels in the image.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: February 16, 2021
    Assignees: APPLIED MATERIALS, INC., APPLIED MATERIALS ISRAEL LTD.
    Inventors: Dror Shemesh, Vadim Kuchik, Nicolas L. Breil
  • Publication number: 20200317708
    Abstract: The present disclosure relates to sugar-linked amino acids and processes for preparing the same. The sugar-linked amino acids may be used for solid-phase peptide synthesis. A sugar compound and an amino acid compound having a nucleophilic side chain are reacted in a heated halogenated solvent. The reaction is catalyst by a Lewis acid, such as InBr3. The reaction is performed as a batch or continuous process.
    Type: Application
    Filed: October 8, 2018
    Publication date: October 8, 2020
    Inventors: Nicola L. POHL, Ravi Kumar HITTANAHALLI KOPPAL VEERA
  • Patent number: 10780309
    Abstract: A barbell comprising a bar member, a first side weight assembly and a second side weight assembly. The bar member has a first side sleeve region and a second side sleeve region opposite the first side sleeve region. The first side weight assembly includes a weight surface and extends over the first side sleeve region, and is rotatively coupled to the bar member through an inner and outer slidable engagement surface. The second side weight assembly includes a weight surface and extends over the second side sleeve region, and is rotatively coupled to the bar member through an inner and outer slidable engagement surface. The bar member includes a first and second surface enhanced region, the first surface enhanced region spanning a portion of the central region and the first side sleeve region, and with the second surface enhanced region spanning a portion of the central region and the second side sleeve region.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: September 22, 2020
    Assignee: Coulter Ventures, LLC
    Inventors: Nicolas L. Garcia, Anahita H. Ameri
  • Patent number: 10707167
    Abstract: An aspect of the invention includes a method for forming a contact in a dielectric layer over a semiconductor substrate. The method may comprise: forming a contact opening in a dielectric layer over the semiconductor substrate to expose an upper portion of the semiconductor substrate; depositing a first liner layer to conformally coat the contact opening; causing a portion of the first liner layer to diffuse into the upper portion of the semiconductor substrate to form a first intermix region at the upper portion of the semiconductor substrate; depositing a refractory metal layer over the first intermix region; and depositing a metal in the contact opening thereby forming the contact.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: July 7, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Emre Alptekin, Nicolas L. Breil, Christian Lavoie, Ahmet S. Ozcan, Kathryn T. Schonenberg
  • Patent number: 10385594
    Abstract: A power locking door handle with capacitive sensing is provided for heavy duty vehicles. The door handle includes a base surface mounted to the exterior of the vehicle door and a hand grip mounted or formed with the base. The handle may be a pull type or push button type. A power lock motor and printed circuit board with a capacitive sensor are sealed within the base. When an operator's hand is inserted between the hand grip and the base, the capacitive sensor sends a signal via the PCB to the motor to unlock the door latch. A key lock cylinder on the base overrides the lock motor if power to the motor is disabled.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: August 20, 2019
    Assignee: TriMark Corporation
    Inventors: David S. Magner, Anita L. Reichling, Nicolas L. Kloxin, Todd Keaffaber, Santosh Balakrishnan
  • Publication number: 20190217147
    Abstract: A barbell comprising a bar member, a first side weight assembly and a second side weight assembly. The bar member has a first side sleeve region and a second side sleeve region opposite the first side sleeve region. The first side weight assembly including a weight surface and extending over the first side sleeve region and coupled rotatively to the bar member through an inner and outer slidable engagement surface. The second side weight assembly including a weight surface and extending over the second side sleeve region and coupled rotatively to the bar member through an inner and outer slidable engagement surface. The bar member includes a first and second surface enhanced region, the first surface enhanced region spanning a portion of the central region and the first side sleeve region, with the second surface enhanced region spanning a portion of the central region and the second side sleeve region.
    Type: Application
    Filed: January 17, 2018
    Publication date: July 18, 2019
    Inventors: Nicolas L. Garcia, Anahita H. Ameri
  • Publication number: 20190053702
    Abstract: Provided are methods for assessment of surface rugosity of a layer of live cells using tools that determine contact angle and contact angle hysteresis.
    Type: Application
    Filed: September 27, 2016
    Publication date: February 21, 2019
    Applicants: The Regents of the University of California, Wisconsin Alumni Research Foundation
    Inventors: Christopher J. MURPHY, Bernardo YAÑEZ-SOTO, Vijay Krishna RAGHUNATHAN, Nicolas L. ABBOTT
  • Publication number: 20190043183
    Abstract: A method for detecting voids in a metal line of a semiconductor device die includes: scanning an electron beam upon a selected location on the die containing the metal line; determine gray levels in an image produced by collected electrons of the electron beam backscattered from the selected location on the die; and identifying one or more voids in the metal line based on differences between the gray levels in the image.
    Type: Application
    Filed: July 31, 2018
    Publication date: February 7, 2019
    Inventors: Dror Shemesh, Vadim Kuchik, Nicolas L. Breil
  • Patent number: 10096609
    Abstract: A method for forming a precision resistor or an e-fuse structure where tungsten silicon is used. The tungsten silicon layer is modified by changing the crystalline structure to a tetragonal tungsten silicon layer.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: October 9, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Nicolas L. Breil, Domingo A. Ferrer, Keith Kwong Hon Wong
  • Publication number: 20180253919
    Abstract: A base control module for vehicles comprises, a controller which includes a housing, a programmable processor, on-board memory, and a plurality of inputs and outputs. The module also comprises, a set of pluggable module interfaces each comprising a standardized connector for any of a plurality of interchangeable pluggable modules, with each pluggable module having a different functionality, and each connector having a plurality of pins. A standardized communication protocol is provided between the base control module and any of the pluggable modules. Adaptable software on the base control module that can assign different configurations for the pins of the connector dependent upon the functionality of the pluggable module for those pins. The same base control module and set of pluggable module interfaces can be used for different pluggable modules.
    Type: Application
    Filed: March 5, 2018
    Publication date: September 6, 2018
    Inventors: David S. Magner, Anita L. Reichling, Nicolas L. Kloxin, Todd Keaffaber, Santosh Balakrishnan, Robert D. Lawson
  • Publication number: 20180252005
    Abstract: A power locking door handle with capacitive sensing is provided for heavy duty vehicles. The door handle includes a base surface mounted to the exterior of the vehicle door and a hand grip mounted or formed with the base. The handle may be a pull type or push button type. A power lock motor and printed circuit board with a capacitive sensor are sealed within the base. When an operator's hand is inserted between the hand grip and the base, the capacitive sensor sends a signal via the PCB to the motor to unlock the door latch. A key lock cylinder on the base overrides the lock motor if power to the motor is disabled.
    Type: Application
    Filed: March 6, 2017
    Publication date: September 6, 2018
    Inventors: David S. Magner, Anita L. Reichling, Nicolas L. Kloxin, Todd Keaffaber, Santosh Balakrishnan