Patents by Inventor Nicolas L. IRIZARRY

Nicolas L. IRIZARRY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12062410
    Abstract: A method, apparatus and system. The method includes: generating a feedback voltage VFB in a feedback circuit coupled to one of a bitline node (BL) or a wordline node (WL) of each of a plurality of memory cells of a memory array, the feedback voltage to, in a thresholded state of said each of the memory cells, counteract a decrease in an absolute value of a voltage Vvdm at said one of the BL or WL; generating, in a reference circuit, one of a reference voltage VREF to track a feedback voltage of the feedback circuit or a mirror current IMFBmirror to track a current Icell through said each of the memory cells; and providing one of values for both VFB and VREF, or for an output voltage Vapsout corresponding to IMFBmirror, to a sense circuitry, the sense circuitry to determine a logic state of said each of the memory cells based on a comparison of VFB with VREF or based on Vapsout.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: August 13, 2024
    Assignee: Intel Corporation
    Inventors: Ashraf B. Islam, Jaydip Bharatkumar Patel, Yasir Mohsin Husain, Balaji Srinivasan, Nicolas L. Irizarry
  • Publication number: 20220270680
    Abstract: Techniques for controlling current through memory cells is disclosed. In the illustrative embodiment, a fine-grained current source and a coarse-grained current source can both be activated to perform an operation on a phase-change memory cell. The coarse-grained current source is briefly activated to charge up the capacitance of an electrical path through the memory cell and then turned off. The fine-grained current source applies a current pulse to perform the operation on the memory cell, such as a reset operation. By charging up the electrical path quickly with the coarse-grained current source, the fine-grained current source can quickly perform the operation on the memory cell, reducing the thermal disturbance caused by the operation on nearby memory cells.
    Type: Application
    Filed: February 24, 2021
    Publication date: August 25, 2022
    Applicant: Intel Corporation
    Inventors: Noble Narku-Tetteh, Yasir Mohsin Husain, Ripudaman Singh, Nicolas L. Irizarry
  • Publication number: 20220180905
    Abstract: A method, apparatus and system. The method includes: generating a feedback voltage VFB in a feedback circuit coupled to one of a bitline node (BL) or a wordline node (WL) of each of a plurality of memory cells of a memory array, the feedback voltage to, in a thresholded state of said each of the memory cells, counteract a decrease in an absolute value of a voltage Vvdm at said one of the BL or WL; generating, in a reference circuit, one of a reference voltage VREF to track a feedback voltage of the feedback circuit or a mirror current IMFBmirror to track a current Icell through said each of the memory cells; and providing one of values for both VFB and VREF, or for an output voltage Vapsout corresponding to IMFBmirror, to a sense circuitry, the sense circuitry to determine a logic state of said each of the memory cells based on a comparison of VFB with VREF or based on Vapsout.
    Type: Application
    Filed: December 7, 2020
    Publication date: June 9, 2022
    Applicant: Intel Corporation
    Inventors: Ashraf B. Islam, Jaydip Bharatkumar Patel, Yasir Mohsin Husain, Balaji Srinivasan, Nicolas L. Irizarry
  • Patent number: 9343119
    Abstract: Embodiments of bus circuits and related techniques are disclosed herein. In some embodiments, a bus circuit may include: a source follower arrangement, including a first transistor and a second transistor, coupled between a supply voltage and an access line of a memory cell, wherein the first transistor and the second transistor each have a gate terminal and wherein the access line is a bit line or a word line; a capacitor having a first terminal coupled to the gate terminal of the first transistor and having a second terminal coupled to a reference voltage; and a switch coupled between the first terminal of the capacitor and a voltage regulator. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: May 17, 2016
    Assignee: Intel Corporation
    Inventors: Nicolas L. Irizarry, Balaji Srinivasan
  • Publication number: 20160071553
    Abstract: Embodiments of bus circuits and related techniques are disclosed herein. In some embodiments, a bus circuit may include: a source follower arrangement, including a first transistor and a second transistor, coupled between a supply voltage and an access line of a memory cell, wherein the first transistor and the second transistor each have a gate terminal and wherein the access line is a bit line or a word line; a capacitor having a first terminal coupled to the gate terminal of the first transistor and having a second terminal coupled to a reference voltage; and a switch coupled between the first terminal of the capacitor and a voltage regulator. Other embodiments may be disclosed and/or claimed.
    Type: Application
    Filed: September 5, 2014
    Publication date: March 10, 2016
    Inventors: Nicolas L. IRIZARRY, Balaji SRINIVASAN