Abstract: There is disclosed a solution for obtaining Memory Access Performance metrics in an electronic system comprising a Data Processing Unit, DPU and a synchronous memory device external to the DPU and coupled to the DPU through a memory bus. There is used mixed software and hardware dedicated resources, wherein at least a hardware part of the dedicated resources is comprised in the memory device.

Abstract: A microprocessor comprises a central processing unit having an arithmetic and logic unit with two inputs and one input fed-back to one of the inputs through a data path. The arithmetic and logic unit performs arithmetic and logic operations on binary words temporarily stored within registers in the central processing unit. The central processing unit further includes a shift unit in the data path of the arithmetic and logic unit for performing operations to shift bits in the binary words applied thereto. A selection circuit selects a shift operation to be performed. An inverting circuit inverts the ordering of the bits in the binary words applied thereto, which are in the data path of the arithmetic and logic unit, and a selection circuit selects the inversion operation when the latter is required.