Abstract: Various exemplary embodiments relate to a patch module connected between a data bus and a ROM memory controller. The patch module may include: at least one patch address register configured to store a ROM address; a patch data register corresponding to each patch address register, each patch data register configured for storing an instruction; an address comparator configured to compare an address received on the data bus with an address stored in each patch address register and output a first signal identifying a matching patch address register and a second signal indicating whether there is a matching address; and a first multiplexer configured to select the patch data register corresponding to the matching patch address register and output the contents of the patch data register to the data bus.

Abstract: A processor circuit is disclosed. In an embodiment, the processor circuit includes a processor unit configured to execute a multiple load or multiple store instruction for loading or storing a plurality of data words, and a data interface block, DIB, configured to communicate with the processor and configured to, in response to an occurrence of an interrupt during execution of the multiple load or store instruction, save the state of the multiple load or store instruction. Saving the state can comprise storing the number of data words already loaded or stored when the interrupt occurred. When the multiple load/store instruction is executed again after the interrupt, the DIB can skip the stored number of data words.

Abstract: A processing system is disclosed. The system comprises: a processing unit; a memory adapted to store firmware code and application code for execution by the processor; and a memory access control unit adapted to control access of the processing unit to firmware code and application code stored in the memory. The memory access control unit is adapted to disable access to firmware code when access to application code is enabled, and to disable access to application code when access to firmware code is enabled.

Abstract: A processor circuit, with: a processor unit configured to execute a multiple load or multiple store instruction for loading or storing a plurality of data words; a data interface block, DIB, configured to communicate with the processor and configured to, in response to an occurrence of an interrupt during execution of the multiple load or store instruction, save the state of the multiple load or store instruction. Saving the state can comprise storing the number of data words already loaded or stored when the interrupt occurred. When the multiple load/store instruction is executed again after the interrupt, the DIB can skip the stored number of data words.

Abstract: Various exemplary embodiments relate to a patch module connected between a data bus and a ROM memory controller. The patch module may include: at least one patch address register configured to store a ROM address; a patch data register corresponding to each patch address register, each patch data register configured for storing an instruction; an address comparator configured to compare an address received on the data bus with an address stored in each patch address register and output a first signal identifying a matching patch address register and a second signal indicating whether there is a matching address; and a first multiplexer configured to select the patch data register corresponding to the matching patch address register and output the contents of the patch data register to the data bus.