Abstract: The invention relates to matrix-array image sensors with MOS-technology active pixels, comprising a matrix-array of pixels arranged in rows and columns. To read the signal from a pixel, the reset potential present on a column conductor is sampled in two capacitors.

Abstract: The invention relates to matrix-array image sensors with MOS-technology active pixels, comprising a matrix-array of pixels arranged in rows and columns. To read the signal from a pixel, the reset potential present on a column conductor is sampled in two capacitors.

Abstract: A self-adaptive method for controlling a self-biased PLL system is disclosed. The method comprises providing an application-dependent input frequency; and providing an application-dependent number N representing the ratio between the output frequency and the application-dependent input frequency to the PLL system. In a system and method in accordance with the present invention, the bandwidth and damping factor are tracked, not only with the input frequency but with the divider ratio as well. Therefore, jitter is minimized for any operating condition (i.e., input frequency variations [N]). The charge-pump current is made to be proportional to the VCO current ID and inversely proportional to the frequency range N; and the loop filter resistor is made to be inversely proportional to the square root of the VCO current ID and proportional to N. In so doing, the bandwidth and damping factors can be tracked more comprehensively.

Abstract: The present invention relates to a phase-locked loop including a comparator and a charge pump. The comparator compares the phases of an input pulse signal and of a reference pulse signal and generates charge and discharge control signals, the charge pump being capable of charging or discharging the capacitive filter according to the charge and discharge control signals. The filter is charged or discharged when these signals are in a first state and insulated from the charge pump when they are in a second state. The loop includes a device for limiting the charge and discharge current of the capacitive filter, this device including windowing circuits for limiting the time during which the charge and discharge control signals are in the first state.

Abstract: A signal treatment circuit treats an input signal containing line sync pulses used for displaying data on a screen. The circuit contains a phase locked loop to control horizontal sweeping according to active edges of line sync pulses, and a filter circuit that filters equalizing signals from the input signals and provides a filtered input signal to the phase locked loop.

Abstract: A device for the generation of a drive signal phase-shifted with respect to an external synchronization signal includes a first digital phase-locked loop to give a reference signal, servo-linked to the external synchronization signal by a current phase among N phases of a high frequency signal. The device includes a second digital phase-locked loop including a measuring circuit to measure the position of an active edge of the drive signal or a derived signal that is delayed with respect to an active edge of the reference signal. The second phase-locked loop also includes a circuit to compute the phase shift to be made and a phase-shift circuit. The measurement circuit includes a circuit for the rough measurement of the position, controlled by a fixed phase of the high frequency signal independent of the present phase of locking in the first loop. The digital computation circuit accounts for this shift between the fixed phase and the present phase.

Abstract: The present invention relates to a circuit for processing vertical synchronization logic signals of positive or negative polarity. Based on signals locating, on the one hand, the presence of the beginning of a pulse and, on the other hand, the rising and falling edges in the synchronization signals, a brief pulse is provided in a signal generated by a one-shot. This pulse induces the generation of edges in signals controlling a latch which generates a logic detection signal. According to the polarity of the received signals, the latch is set or reset and the state of the detection signal indicates the polarity of the synchronization signals.

Abstract: The present invention relates to a device for detecting the locking of an automatic gain control circuit, the automatic gain control circuit receiving a signal to be regulated, a check signal and a sampling control signal for driving the operation of the circuit. The detection device includes a comparator receiving the check signal and the signal to be regulated or a signal representative of the signal to be regulated. The comparator generates two logic signals, the states of which form a specific combination of logic states when the value of the signal to be regulated is in a range of values including the value of the check signal. A logic comparator circuit generates a logic comparison signal, the state of which is representative of the presence or absence of this specific combination, and a storage means, driven by the sampling control signal, stores the state of the signal provided by the logic circuit.

Abstract: A device for correcting the linearity of ramps of a saw-tooth signal provided across a capacitor, charged by a first current source and periodically discharged at a desired frequency. The device modulates the charging current of the capacitor by a correction current to render the ramps of the signal not linear. In addition, the device includes circuitry to render the correction current proportional to the current provided by the first current source.