Abstract: The invention concerns a device including: first and second detectors of the phase and/or of the frequency of an input signal with respect to first and second reference signals; and a Sigma/Delta converter interpreting outputs of the first or of the second phase and/or frequency detector to determine a propagation time of the input signal.

Abstract: A method is disclosed for operating an imaging device having a matrix of pixels arranged in rows and columns. A polarization voltage is generated on a gate of a main MOS transistor that is connected as diode. The main MOS transistor is coupled between a power supply voltage and a ground circuit. Prior to reading the pixels of a row of the matrix, a plurality of first capacitors are charged with the polarization voltage. The first capacitors are coupled between the gate of the main transistor and a ground node. Upon reading the pixels of the row, the first capacitors are discharged on respective gates of auxiliary transistors coupled between the columns and the ground node so as to switch on the auxiliary transistors and deliver a substantially identical polarization current to each column.

Abstract: A laser diode driver circuit includes a first pair of contacts and connectors coupled to an anode of the laser diode. An inductance of each of the first pair of contacts and connectors is the same. A second pair of contacts and connectors are coupled to a cathode of the laser diode. An inductance of each of the second pair of contacts and connectors is the same. The laser diode driver circuit also includes current driving circuitry.

Abstract: A circuit includes a laser diode and a switched-capacitance charge pump coupled to control the laser diode. The charge pump can include a capacitor and a switching circuit that is capable of triggering a charge and discharge of the capacitor. The switching circuit can include a switch and an inverting circuit.

Abstract: The invention concerns a device including: first and second detectors of the phase and/or of the frequency of an input signal with respect to first and second reference signals; and a Sigma/Delta converter interpreting outputs of the first or of the second phase and/or frequency detector to determine a propagation time of the input signal.

Abstract: Disclosed herein is a method of optical pulse emission including three phases. During a first phase, a capacitor is charged from a supply voltage node. During a second phase, a voltage stored on the capacitor is boosted, and then the capacitor is at least partially discharged through a light emitting device. During a third phase, the capacitor is further discharged by bypassing the light emitting device. The third phase may begin prior to an end of the second phase.

Abstract: An optical pulse emitter includes a light emitting device having a first node coupled to an intermediate node via a first switch. The intermediate node is coupled to a supply voltage node via a second switch. A capacitor is coupled to the intermediate node. The first, second and third switches are controlled by a control circuit. During a first phase, the second switch is actuated to couple the capacitor to the supply voltage node. During a second phase, the second switch is deactuated and the first switch is actuated to at least partially discharge the capacitor through the light emitting device. During a third phase, discharge current from the capacitor bypasses around the light emitting device.

Abstract: A method is disclosed for operating an imaging device having a matrix of pixels arranged in rows and columns. A polarization voltage is generated on a gate of a main MOS transistor that is connected as diode. The main MOS transistor is coupled between a power supply voltage and a ground circuit. Prior to reading the pixels of a row of the matrix, a plurality of first capacitors are charged with the polarization voltage. The first capacitors are coupled between the gate of the main transistor and a ground node. Upon reading the pixels of the row, the first capacitors are discharged on respective gates of auxiliary transistors coupled between the columns and the ground node so as to switch on the auxiliary transistors and deliver a substantially identical polarization current to each column.

Abstract: A method can be used to generate a reference clock signal having a reference frequency. N clock sub-signals are generated, where N is greater than or equal to 2. The N clock sub-signals are successively mutually shifted out of phase by ?/N and each clock sub-signal has an elementary frequency that is equal to the reference frequency divided by N. The N clock sub-signals are propagated over propagation paths. The elementary frequency and a length of the longest propagation path are chosen so that each sub-signal has an acceptable degree of deformation. The duration of each sub-signal edge is longer than quarter of the period of the reference frequency. The reference clock signal is generated by EXCLUSIVE OR combining the propagated clock sub-signals at the end of their respective propagation paths.

Abstract: A method can be used to generate a reference clock signal having a reference frequency. N clock sub-signals are generated, where N is greater than or equal to 2. The N clock sub-signals are successively mutually shifted out of phase by ?/N and each clock sub-signal has an elementary frequency that is equal to the reference frequency divided by N. The N clock sub-signals are propagated over propagation paths. The elementary frequency and a length of the longest propagation path are chosen so that each sub-signal has an acceptable degree of deformation. The duration of each sub-signal edge is longer than quarter of the period of the reference frequency. The reference clock signal is generated by EXCLUSIVE OR combining the propagated clock sub-signals at the end of their respective propagation paths.

Abstract: A device for conversion of an analog signal into a digital signal includes a clock signal generator and a ramp generator configured for delivering a rising voltage ramp. A comparator is configured for comparing the value of the analog signal and the value of the voltage ramp and for generating a comparison signal taking a first logical value when the two values are equal. A signal generator is configured for generating a counter signal equal to the inverse of the clock signal if the comparison signal takes its first value while the clock signal is in the high state, or a counter signal equal to the clock signal if the clock signal is in the low state. A counter is configured for counting the number of edges of the counter signal.

Abstract: A CMOS image sensor including: an array of M×N pixels, the pixels of a same column being connected to a same output track, each pixel including a photodiode, a sense node, a transfer transistor, a reset transistor, and a read circuit; and a test circuit including an assembly of N elementary reference cells respectively connected to the N output tracks of the sensor, each cell including a resistor, a sense node, a transfer transistor, a reset transistor, and a read circuit, the N resistors being series-connected between first and second nodes of application of a reference voltage.

Abstract: An optical pulse emitter includes a light emitting device having a first node coupled to an intermediate node via a first switch. The intermediate node is coupled to a supply voltage node via a second switch. A capacitor is coupled to the intermediate node. The first, second and third switches are controlled by a control circuit. During a first phase, the second switch is actuated to couple the capacitor to the supply voltage node. During a second phase, the second switch is deactuated and the first switch is actuated to at least partially discharge the capacitor through the light emitting device. During a third phase, discharge current from the capacitor bypasses around the light emitting device.

Abstract: A CMOS image sensor including: an array of M×N pixels, the pixels of a same column being connected to a same output track, each pixel including a photodiode, a sense node, a transfer transistor, a reset transistor, and a read circuit; and a test circuit including an assembly of N elementary reference cells respectively connected to the N output tracks of the sensor, each cell including a resistor, a sense node, a transfer transistor, a reset transistor, and a read circuit, the N resistors being series-connected between first and second nodes of application of a reference voltage.

Abstract: An audio receiver system including: a modulator (1) for modulating a first digital audio signal with a first modulation rate and a second digital audio signal including a plurality of 1-bit words over a predetermined period at a second modulation rate higher than the first modulation rate, and an output device (11) including a loudspeaker (10) and a transmitter for transmitting the second signal in analog form to the loudspeaker (10), characterized in that it further includes a control device (2) connected to the modulator (1) and receiving the signal from it and to the output device (11), the control device is adapted to control the output device (11) from a portion-of said predetermined period, and the length of said portion is determined as a function of the required volume.