Abstract: There is disclosed the integration of a Schottky diode with a MOSFET, more in detail there is a free-wheeling Schottky diode and a power MOSFET on top of a buried grid material structure. Advantages of the specific design allow the whole surface area to be used for MOSFET and Schottky diode structures, the shared drift layer is not limited by Schottky diode or MOSFET design rules and therefore, one can decrease the thickness and increase the doping concentration of the drift layer closer to a punch through design compared to the state of the art. This results in higher conductivity and lower on-resistance of the device with no influence on the voltage blocking performance. The integrated device can operate at higher frequency. The risk for bipolar degradation is avoided.

Abstract: A grid is manufactured with a combination of ion implant and epitaxy growth. The grid structure is made in a SiC semiconductor material with the steps of a) providing a substrate comprising a doped semiconductor SiC material, said substrate comprising a first layer (n1), b) by epitaxial growth adding at least one doped semiconductor SiC material to form separated second regions (p2) on the first layer (n1), if necessary with aid of removing parts of the added semiconductor material to form separated second regions (p2) on the first layer (n1), and c) by ion implantation at least once at a stage selected from the group consisting of directly after step a), and directly after step b); implanting ions in the first layer (n1) to form first regions (p1). It is possible to manufacture a grid with rounded corners as well as an upper part with a high doping level.

Abstract: There is disclosed a method for manufacturing a MOSFET with lateral channel in SiC, said MOSFET comprising simultaneously formed n type regions comprising an access region and a JFET region defining the length of the MOS channel, and wherein the access region and the JFET region are formed by ion implantation by using one masking step. The design is self-aligning so that the length of the MOS channel is defined by simultaneous creating n-type regions on both sides of the channel using one masking step. Any misalignment in the mask is moved to other less critical positions in the device. The risk of punch-through is decreased compared to the prior art. The current distribution becomes more homogenous. The short-circuit capability increases. There is lower Drain-Source specific on-resistance due to a reduced MOS channel resistance. There is a lower JFET resistance due to the possibility to increase the JFET region doping concentration.

Abstract: A method for automatically optimizing a 3D textured model for network transfer and real-time rendering is based on a quadric simplification algorithm allowing any user to obtain transparently a real-time rendering of a 3D textured model. The algorithm is performed by using predefined heuristics, and is associated with a plurality of simplified versions of the 3D model, each simplified version being associated with a predefined level of detail adapted to the user specific environment.

Abstract: A method of handling content in a computer device allows creating on a computer device a model with a local application and transferring the model directly into a local web browser of the computer device and vice-versa, without any transfer of data via a distant server, or without any local disk transfer on the computer device.

Abstract: A method for automatically optimizing a 3D textured model for network transfer and real-time rendering is based on a quadric simplification algorithm allowing any user to obtain transparently a real-time rendering of a 3D textured model. The algorithm is performed by using predefined heuristics, and is associated with a plurality of simplified versions of the 3D model, each simplified version being associated with a predefined level of detail adapted to the user specific environment.