Patents by Inventor Nicolas Vantalon
Nicolas Vantalon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10502838Abstract: Methods, systems, and devices for monitoring a Real Time Clock (RTC) oscillator using Digital Signal Processing (DSP), where a resistance/capacitance (RC) oscillator is configured to output a digital pulse signal and a digital RTC Monitor Integrated Circuit (IC) is configured to monitor the RTC oscillator timing signal using the RC oscillator signal. In one aspect, the RTC Monitor IC includes an RTC input configured to receive the RTC oscillator timing signal; an RC input configured to receive the RC oscillator digital pulse signal; and an RTC reset output configured to output an RTC reset signal when a comparison of the RTC and RC oscillator inputs show the RTC oscillator has missed one or more clock cycles. A single wire input/output for both reset and interrupt signals between circuits is also described.Type: GrantFiled: May 10, 2017Date of Patent: December 10, 2019Assignee: Samsung Electronics Co., LtdInventors: Daniel Babitch, Steven A Gronemeyer, Nicolas Vantalon
-
Publication number: 20170242130Abstract: Methods, systems, and devices for monitoring a Real Time Clock (RTC) oscillator using Digital Signal Processing (DSP), where a resistance/capacitance (RC) oscillator is configured to output a digital pulse signal and a digital RTC Monitor Integrated Circuit (IC) is configured to monitor the RTC oscillator timing signal using the RC oscillator signal. In one aspect, the RTC Monitor IC includes an RTC input configured to receive the RTC oscillator timing signal; an RC input configured to receive the RC oscillator digital pulse signal; and an RTC reset output configured to output an RTC reset signal when a comparison of the RTC and RC oscillator inputs show the RTC oscillator has missed one or more clock cycles. A single wire input/output for both reset and interrupt signals between circuits is also described.Type: ApplicationFiled: May 10, 2017Publication date: August 24, 2017Inventors: Daniel BABITCH, Steven A. GRONEMEYER, Nicolas VANTALON
-
Patent number: 9651676Abstract: Methods, systems, and devices for monitoring a Real Time Clock (RTC) oscillator using Digital Signal Processing (DSP), where a resistance/capacitance (RC) oscillator is configured to output a digital pulse signal and a digital RTC Monitor Integrated Circuit (IC) is configured to monitor the RTC oscillator timing signal using the RC oscillator signal. In one aspect, the RTC Monitor IC includes an RTC input configured to receive the RTC oscillator timing signal; an RC input configured to receive the RC oscillator digital pulse signal; and an RTC reset output configured to output an RTC reset signal when a comparison of the RTC and RC oscillator inputs show the RTC oscillator has missed one or more clock cycles. A single wire input/output for both reset and interrupt signals between circuits is also described.Type: GrantFiled: July 10, 2014Date of Patent: May 16, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Daniel Babitch, Steven A Gronemeyer, Nicolas Vantalon
-
Patent number: 9644971Abstract: A Micro-Electromechanical System (MEMS) recorder is provided. The MEMS recorder includes a scheduler, a serializer, a multiplexer, a transmit/receive switch, a master clock generator, a deserializer, a comparator array to determine whether to generate a signal to wake up a controller and/or a location module from a sleep mode, and a First-In-First-Out (FIFO) memory to output data to be stored and wake up the controller and/or the location module from the sleep mode if a signal to wake up the controller and/or the location module is received or if the FIFO memory is full, wherein the controller and/or the location module is awakened directly by the MEMS recorder or via the controller.Type: GrantFiled: November 4, 2014Date of Patent: May 9, 2017Assignee: Samsung Electronics Co., LtdInventors: Daniel Babitch, Nicolas Vantalon
-
Publication number: 20170024345Abstract: A Micro-Electromechanical System (MEMS) recorder is provided. The MEMS recorder includes a scheduler, a serializer, a multiplexer, a transmit/receive switch, a master clock generator, a deserializer, a comparator array to determine whether to generate a signal to wake up a controller and/or a location module from a sleep mode, and a First-In-First-Out (FIFO) memory to output data to be stored and wake up the controller and/or the location module from the sleep mode if a signal to wake up the controller and/or the location module is received or if the FIFO memory is full, wherein the controller and/or the location module is awakened directly by the MEMS recorder or via the controller.Type: ApplicationFiled: November 4, 2014Publication date: January 26, 2017Inventors: Daniel BABITCH, Nicolas Vantalon
-
Publication number: 20150097726Abstract: Methods, systems, and devices for monitoring a Real Time Clock (RTC) oscillator using Digital Signal Processing (DSP), where a resistance/capacitance (RC) oscillator is configured to output a digital pulse signal and a digital RTC Monitor Integrated Circuit (IC) is configured to monitor the RTC oscillator timing signal using the RC oscillator signal. In one aspect, the RTC Monitor IC includes an RTC input configured to receive the RTC oscillator timing signal; an RC input configured to receive the RC oscillator digital pulse signal; and an RTC reset output configured to output an RTC reset signal when a comparison of the RTC and RC oscillator inputs show the RTC oscillator has missed one or more clock cycles. A single wire input/output for both reset and interrupt signals between circuits is also described.Type: ApplicationFiled: July 10, 2014Publication date: April 9, 2015Inventors: Daniel Babitch, Steven A. GRONEMEYER, Nicolas VANTALON
-
Patent number: 8593345Abstract: A signal processing system for processing satellite positioning signals is described. The system comprises at least one processor and a signal processor operating under a number of operational modes. The signal processor includes at least one of a signal processing subsystem, a fast Fourier transform (FFT) subsystem, and a memory subsystem that are each dynamically and independently configurable in response to the operational modes. Further, the system includes a controller that couples to control transfer of data among the signal processing subsystem and the FFT subsystem via the memory subsystem. Configurability of the memory subsystem includes configuring the memory subsystem into regions according to the operational modes where each region is accessible in one of a number of manners according to the operational modes.Type: GrantFiled: February 20, 2012Date of Patent: November 26, 2013Assignee: CSR Technology Inc.Inventors: Paul A. Underbrink, Henry D. Falk, Steven A. Gronemeyer, Chittharanjan Dassannacharya, Charles P. Norman, Nicolas Vantalon, Vojislav Protic
-
Publication number: 20120313817Abstract: A signal processing system for processing satellite positioning signals is described. The system comprises at least one processor and a signal processor operating under a number of operational modes. The signal processor includes at least one of a signal processing subsystem, a fast Fourier transform (FFT) subsystem, and a memory subsystem that are each dynamically and independently configurable in response to the operational modes. Further, the system includes a controller that couples to control transfer of data among the signal processing subsystem and the FFT subsystem via the memory subsystem. Configurability of the memory subsystem includes configuring the memory subsystem into regions according to the operational modes where each region is accessible in one of a number of manners according to the operational modes.Type: ApplicationFiled: February 20, 2012Publication date: December 13, 2012Applicant: CSR Technology Inc.Inventors: Paul A. Underbrink, Henry D. Falk, Steven A. Gronemeyer, Chittharanjan A. Dasannacharya, Charles P. Norman, Nicolas Vantalon, Vojislav Protic
-
Patent number: 8138972Abstract: A signal processing system for processing satellite positioning signals is described. The system comprises at least one processor and a signal processor operating under a number of operational modes. The signal processor includes at least one of a signal processing subsystem, a fast Fourier transform (FFT) subsystem, and a memory subsystem that are each dynamically and independently configurable in response to the operational modes. Further, the system includes a controller that couples to control transfer of data among the signal processing subsystem and the FFT subsystem via the memory subsystem. Configurability of the memory subsystem includes configuring the memory subsystem into regions according to the operational modes where each region is accessible in one of a number of manners according to the operational modes.Type: GrantFiled: September 2, 2004Date of Patent: March 20, 2012Assignee: CSR Technology Inc.Inventors: Paul A. Underbrink, Henry D. Falk, Steven A. Gronemeyer, Chittharanjan A. Dassannacharya, Charles P. Norman, Nicolas Vantalon, Vojislav Protic
-
Publication number: 20110102258Abstract: A signal processing system for processing satellite positioning signals is described. The system comprises at least one processor and a signal processor operating under a number of operational modes. The signal processor includes at last one of a signal processing subsystem, a fast Fourier transform (FFT) subsystem, and a memory subsystem that are each dynamically and independently configurable in response to the operational modes. Further, the system includes a controller that couples to control transfer of data among the signal processing subsystem and the FFT subsystem via the memory subsystem. Configurability of the memory subsystem includes configuring the memory subsystem into regions according to the operational modes where each region is accessible in one of a number of manners according to the operational modes.Type: ApplicationFiled: September 2, 2004Publication date: May 5, 2011Applicant: SIRF TECHNOLOGY, INC.Inventors: Paul A. Underbrink, Henry D. Falk, Steven A. Gronemeyer, Chittharanjan Dassannacharya, Charles P. Norman, Nicolas Vantalon, Vojislav Protic
-
Publication number: 20070008218Abstract: A tracker architecture for Global Positioning System (GPS) receivers is disclosed. A typical tracker comprises an RF front end and GPS architecture. The architecture comprises a bus structure, a Central Processing Unit (CPU) core, cache, RAM, and ROM memories, and a GPS engine that comprises a receiving, tracking, and demodulating engine for GPS and Wide Area Augmentation Service (WAAS) signals. The GPS architecture can couple to at least two different protocol interfaces via the bus structure, where the protocol interfaces are commonly used in different applications.Type: ApplicationFiled: June 26, 2006Publication date: January 11, 2007Inventors: Nicolas Vantalon, Leon Peng, Gregory Turetzky
-
Publication number: 20060248289Abstract: Memory reallocation and sharing among components of an electronic system is provided. The electronic system includes a first memory area coupled for access by a first processor via a first bus, and a second memory area coupled for access by a second processor via a second bus. An example system includes a central processor as the first processor and a digital signal processor as the second processor. The electronic system further includes memory configurations that support shared access of the second memory area by the first processor. Using shared access, the first processor can directly access the second memory via the first bus or indirectly access the second memory via the second bus and the second processor. The memory sharing also includes partitioning the shared memory to simultaneously provide the first processor with direct and indirect access to the shared memory.Type: ApplicationFiled: March 6, 2006Publication date: November 2, 2006Inventors: Nicolas Vantalon, Steven Gronemeyer, Vojislav Protic
-
Patent number: 7091904Abstract: A tracker architecture for Global Positioning System (GPS) receivers is disclosed. A typical tracker comprises an RF front end and GPS architecture. The architecture comprises a bus structure, a Central Processing Unit (CPU) core, cache, RAM, and ROM memories, and a GPS engine that comprises a receiving, tracking, and demodulating engine for GPS and Wide Area Augmentation Service (WAAS) signals. The GPS architecture can couple to at least two different protocol interfaces via the bus structure, where the protocol interfaces are commonly used in different applications.Type: GrantFiled: July 18, 2002Date of Patent: August 15, 2006Assignee: SiRF Technology, Inc.Inventors: Nicolas Vantalon, Leon Kuo-Liang Peng, Gregory Turetzky
-
Publication number: 20060095206Abstract: The invention relates to an aided Global Positioning System (GPS) subsystem within a wireless device. The wireless device includes a wireless processing section capable of receiving signals from a wireless network and a GPS subsystem having a radio frequency (RF) front-end capable of receiving a GPS satellite signal. The wireless processing section of the wireless device receives an external clock and determines the offset between the clock in the wireless processing section and that of the external clock. The GPS subsystem then receives the offset information from the wireless processing section, information related to the nominal frequency of the wireless processing section clock and the wireless processing section clock. Using this information and the GPS clock in the GPS subsystem, the GPS subsystem determines an acquiring signal, which is related to a frequency offset between the GPS clock and the network clock.Type: ApplicationFiled: May 22, 2003Publication date: May 4, 2006Inventors: Lionel Garin, Leon Peng, Gengsheng Zhang, Nicolas Vantalon
-
Publication number: 20060038719Abstract: An Aided Location Communication System (“ALCS”) is described that may include a geolocation server and a wireless communication device having a GPS section where the GPS receiver section is capable of being selectively switched between a standalone mode and at least one other mode for determining a geolocation of the wireless communications device. An Aided Location Communication Device (“ALCD”) is also described. The ALCD includes a position-determination section having a GPS receiver and a communication section where the position-determination section is selectively switchable between a GPS-standalone mode and at least one other mode for determining a geolocation of the ALCD.Type: ApplicationFiled: July 20, 2005Publication date: February 23, 2006Inventors: Ashutosh Pande, Lionel Garin, Kanwar Chadha, Kurt Schmidt, Leon Peng, Gengsheng Zhang, Nicolas Vantalon, Gregory Turetzky
-
Publication number: 20050227709Abstract: In a method for providing location-based information over a network, a plurality of GPS reference data sets, corresponding to a plurality of respective local areas, are acquired at intervals such that each GPS reference data set is updated on a continuous basis. A plurality of aiding data sets are generated at intervals based on the respective GPS data sets, whereby each aiding data set is updated on a continuous basis. The generated aiding data sets are stored at intervals on a data-storing network server, whereby updated aiding data sets are available on a continuous basis for access by a requesting entity via communication with the data-storing network server.Type: ApplicationFiled: March 24, 2005Publication date: October 13, 2005Inventors: Steve Chang, Ashutosh Pande, Lionel Garin, Kanwar Chadha, Leon Peng, Gengsheng Zhang, Nicolas Vantalon, Gregory Turetsky
-
Publication number: 20050162306Abstract: A frequency phase correction system and method are described that provides a receiver with a greater ability to lock onto relatively weak radio frequency signals by determining and estimating an amount of frequency error in a local frequency reference of the receiver, and using the error estimate to maintain frequency coherence with a received signal, thereby allowing tracking over a longer period of time, enabling longer integration times to capture weaker signals without losing frequency coherence.Type: ApplicationFiled: November 24, 2004Publication date: July 28, 2005Inventors: Daniel Babitch, Steven Gronemeyer, Lionel Garin, Ashutosh Pande, Leon Peng, Gengsheng Zhang, Nicolas Vantalon
-
Publication number: 20050062643Abstract: An Aided Location Communication System (“ALCS”) is described that may include a geolocation server and a wireless communication device having a GPS section where the GPS receiver section is capable of being selectively switched between a standalone mode and at least one other mode for determining a geolocation of the wireless communications device. An Aided Location Communication Device (“ALCD”) is also described. The ALCD includes a position-determination section having a GPS receiver and a communication section where the position-determination section is selectively switchable between a GPS-standalone mode and at least one other mode for determining a geolocation of the ALCD.Type: ApplicationFiled: July 3, 2004Publication date: March 24, 2005Inventors: Ashutosh Pande, Lionel Garin, Kanwar Chadha, Kurt Schmidt, Leon Peng, Gengsheng Zhang, Nicolas Vantalon, Gregory Turetzky
-
Publication number: 20050050282Abstract: Memory reallocation and sharing among components of an electronic system is provided. The electronic system includes a first memory area coupled for access by a first processor via a first bus, and a second memory area coupled for access by a second processor via a second bus. An example system includes a central processor as the first processor and a digital signal processor as the second processor. The electronic system further includes memory configurations that support shared access of the second memory area by the first processor. Using shared access, the first processor can directly access the second memory via the first bus or indirectly access the second memory via the second bus and the second processor. The memory sharing also includes partitioning the shared memory to simultaneously provide the first processor with direct and indirect access to the shared memory.Type: ApplicationFiled: October 28, 2003Publication date: March 3, 2005Inventors: Nicolas Vantalon, Steven Gronemeyer, Vojislav Protic
-
Publication number: 20040252049Abstract: A tracker architecture for Global Positioning System (GPS) receivers is disclosed. A typical tracker comprises an RF front end and GPS architecture. The architecture comprises a bus structure, a Central Processing Unit (CPU) core, cache, RAM, and ROM memories, and a GPS engine that comprises a receiving, tracking, and demodulating engine for GPS and Wide Area Augmentation Service (WAAS) signals. The GPS architecture can couple to at least two different protocol interfaces via the bus structure, where the protocol interfaces are commonly used in different applications.Type: ApplicationFiled: July 18, 2002Publication date: December 16, 2004Inventors: Nicolas Vantalon, Leon Kuo-Liang Peng, Gregory Turetzky