Abstract: Various systems and methods for virtual CPU consolidation to avoid physical CPU contention between virtual machines are described herein. A processor system that includes multiple physical processors (PCPUs) includes a first virtual machine (VM) that includes multiple first virtual processors (VCPUs); a second VM that includes multiple second VCPUs; and a virtual machine monitor (VMM) to map individual ones of the first VCPUs to run on at least one of, individual PCPUs of a first subset of the PCPUs and individual PCPUs of a set of PCPUs that includes the first subset of the PCPUs and a second subset of the PCPUs, based at least in part upon compute capacity of the first subset of the PCPUs to run the first VCPUs, and to map individual ones of the second VCPUs to run on individual ones of the second subset of the PCPUs.

Abstract: Various systems and methods for virtual CPU consolidation to avoid physical CPU contention between virtual machines are described herein. A processor system that includes multiple physical processors (PCPUs) includes a first virtual machine (VM) that includes multiple first virtual processors (VCPUs); a second VM that includes multiple second VCPUs; and a virtual machine monitor (VMM) to map individual ones of the first VCPUs to run on at least one of, individual PCPUs of a first subset of the PCPUs and individual PCPUs of a set of PCPUs that includes the first subset of the PCPUs and a second subset of the PCPUs, based at least in part upon compute capacity of the first subset of the PCPUs to run the first VCPUs, and to map individual ones of the second VCPUs to run on individual ones of the second subset of the PCPUs.

Abstract: An optimal idle state of a processor is selected using dynamically derived parameters. For example, the idle state is selected from a group of possible idle power states. A current detector is arranged to perform power measurements of the processor and to report a total power consumption of the processor for each time value of a range of discrete values for each possible idle power state. A calibration unit is arranged to communicate with the current detector and the processor, and to automatically activate a calibration sequence that is used to produce data from which idle power state is optimal for the processor for an estimated idle period.

Abstract: An optimal idle state of a processor is selected using dynamically derived parameters. For example, the idle state is selected from a group of possible idle power states. A current detector is arranged to perform power measurements of the processor and to report a total power consumption of the processor for each time value of a range of discrete values for each possible idle power state. A calibration unit is arranged to communicate with the current detector and the processor, and to automatically activate a calibration sequence that is used to produce data from which idle power state is optimal for the processor for an estimated idle period.

Abstract: An optimal idle state of a processor is selected using dynamically derived parameters. For example, the idle state is selected from a group of possible idle power states. A current detector is arranged to perform power measurements of the processor and to report a total power consumption of the processor for each time value of a range of discrete values for each possible idle power state. A calibration unit is arranged to communicate with the current detector and the processor, and to automatically activate a calibration sequence that is used to produce data from which idle power state is optimal for the processor for an estimated idle period.

Abstract: An optimal idle state of a processor is selected using dynamically derived parameters. For example, the idle state is selected from a group of possible idle power states. A current detector is arranged to perform power measurements of the processor and to report a total power consumption of the processor for each time value of a range of discrete values for each possible idle power state. A calibration unit is arranged to communicate with the current detector and the processor, and to automatically activate a calibration sequence that is used to produce data from which idle power state is optimal for the processor for an estimated idle period.

Abstract: Displaying a stream of video data on a display device may be performed by decoding a portion of the video data to form a video frame. A queue time is determined when the video frame should be displayed. The queue time is adjusted by a margin time relative to a next display time to compensate for interrupt jitter, wherein the margin time is less than a period of time between periodic display time events and is larger than a specified interrupt jitter time. A software interrupt event is set to occur corresponding to the adjusted queue time. The video frame is queued in response to occurrence of the software interrupt. The queued video frame is transferred to a display buffer for the display device upon the occurrence of a next display time event after the occurrence of the software interrupt.