Patents by Inventor Nicole Gerrish

Nicole Gerrish has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9219065
    Abstract: A method of fabricating a circuit comprising an nMOSFET includes providing a substrate, depositing a strain-inducing material comprising germanium over the substrate, and integrating a pMOSFET on the substrate, the pMOSFET comprising a strained channel having a surface roughness of less than 1 nm. The strain-inducing material is proximate to and in contact with the pMOSFET channel, the strain in the pMOSFET channel is induced by the strain-inducing material, and a source and a drain of the pMOSFET are at least partially formed in the strain-inducing material.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: December 22, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eugene A. Fitzgerald, Nicole Gerrish
  • Publication number: 20060275972
    Abstract: A method of fabricating a CMOS inverter including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained surface layer on said relaxed Si1-xGex layer; and integrating a pMOSFET and an nMOSFET in said heterostructure, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides a method of fabricating an integrated circuit including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained layer on the relaxed Si1-xGex layer; and forming a p transistor and an n transistor in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor interconnected in a CMOS circuit.
    Type: Application
    Filed: May 10, 2006
    Publication date: December 7, 2006
    Applicant: AmberWave Systems Corporation
    Inventors: Eugene Fitzgerald, Nicole Gerrish
  • Publication number: 20050106850
    Abstract: A method of fabricating a CMOS inverter including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained surface layer on said relaxed Si1-xGex layer; and integrating a pMOSFET and an nMOSFET in said heterostructure, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides a method of fabricating an integrated circuit including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained layer on the relaxed Si1-xGex layer; and forming a p transistor and an n transistor in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.
    Type: Application
    Filed: September 29, 2004
    Publication date: May 19, 2005
    Applicant: AmberWave Systems Corporation
    Inventors: Eugene Fitzgerald, Nicole Gerrish
  • Patent number: 6881632
    Abstract: A method of fabricating a CMOS inverter including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained surface layer on said relaxed Si1-xGex layer; and integrating a pMOSFET and an nMOSFET in said heterostructure, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides a method of fabricating an integrated circuit including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained layer on the relaxed Si1-xGex layer; and forming a p transistor and an n transistor in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.
    Type: Grant
    Filed: July 1, 2003
    Date of Patent: April 19, 2005
    Assignee: AmberWave Systems Corporation
    Inventors: Eugene A. Fitzgerald, Nicole Gerrish
  • Publication number: 20040097025
    Abstract: A method of fabricating a CMOS inverter including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained surface layer on said relaxed Si1-xGex layer; and integrating a pMOSFET and an nMOSFET in said heterostructure, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides a method of fabricating an integrated circuit including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained layer on the relaxed Si1-xGex layer; and forming a p transistor and an n transistor in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.
    Type: Application
    Filed: July 1, 2003
    Publication date: May 20, 2004
    Applicant: AmberWave Systems Corporation
    Inventors: Eugene A. Fitzgerald, Nicole Gerrish
  • Publication number: 20040075149
    Abstract: A CMOS inverter having a heterostructure including a Si substrate, a relaxed Si1−xGex layer on the Si substrate, and a strained surface layer on said relaxed Si1−xGex layer; and a pMOSFET and an nMOSFET, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides an integrated circuit having a heterostructure including a Si substrate, a relaxed Si1−xGex layer on the Si substrate, and a strained layer on the relaxed Si1−xGex layer; and a p transistor and an n transistor formed in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.
    Type: Application
    Filed: July 23, 2003
    Publication date: April 22, 2004
    Applicant: Amberwave Systems Corporation
    Inventors: Eugene A. Fitzgerald, Nicole Gerrish
  • Patent number: 6649480
    Abstract: A method of fabricating a CMOS inverter including providing a heterostructure having a Si substrate, a relaxed Si1-x Gex layer on the Si substrate, and a strained surface layer on said relaxed Si1-x Gex layer; and integrating a pMOSFET and an nMOSFET in said heterostructure, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides a method of fabricating an integrated circuit including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained layer on the relaxed Si1-x Gex layer; and forming a p transistor and an n transistor in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: November 18, 2003
    Assignee: AmberWave Systems Corporation
    Inventors: Eugene A. Fitzgerald, Nicole Gerrish
  • Publication number: 20030034529
    Abstract: A CMOS inverter having a heterostructure including a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained surface layer on said relaxed Si1-xGex layer; and a pMOSFET and an nMOSFET, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides an integrated circuit having a heterostructure including a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained layer on the relaxed Si1-xGex layer; and a p transistor and an n transistor formed in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.
    Type: Application
    Filed: October 8, 2002
    Publication date: February 20, 2003
    Applicant: Amberwave Systems Corporation
    Inventors: Eugene A. Fitzgerald, Nicole Gerrish
  • Publication number: 20020125471
    Abstract: A CMOS inverter having a heterostructure including a Si substrate, a relaxed Si1−xGex, layer on the Si substrate, and a strained surface layer on said relaxed Si1−xGex, layer; and a pMOSFET and an nMOSFET, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides an integrated circuit having a heterostructure including a Si substrate, a relaxed Si1−xGex, layer on the Si substrate, and a strained layer on the relaxed Si1−xGex, layer; and a p transistor and an n transistor formed in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.
    Type: Application
    Filed: December 4, 2001
    Publication date: September 12, 2002
    Inventors: Eugene A. Fitzgerald, Nicole Gerrish
  • Publication number: 20020123197
    Abstract: A method of fabricating a CMOS inverter including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained surface layer on said relaxed Si1-xGex layer; and integrating a pMOSFET and an nMOSFET in said heterostructure, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides a method of fabricating an integrated circuit including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained layer on the relaxed Si1-xGex layer; and forming a p transistor and an n transistor in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.
    Type: Application
    Filed: June 19, 2001
    Publication date: September 5, 2002
    Inventors: Eugene A. Fitzgerald, Nicole Gerrish
  • Publication number: 20020100942
    Abstract: A CMOS inverter having a heterostructure including a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained surface layer on said relaxed Si1-xGex layer; and a pMOSFET and an nMOSFET, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides an integrated circuit having a heterostructure including a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained layer on the relaxed Si1-xGex layer; and a p transistor and an n transistor formed in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.
    Type: Application
    Filed: June 19, 2001
    Publication date: August 1, 2002
    Inventors: Eugene A. Fitzgerald, Nicole Gerrish