Abstract: In one embodiment, an integrated circuit structure includes a first transistor device comprising a first gate stack and a second transistor device comprising a second gate stack. The second transistor device is spaced a first distance laterally from the first transistor device. The structure further includes a dielectric region between the first gate stack and the second gate stack. The dielectric region is spaced a second distance laterally from the first transistor device, where the first distance is substantially twice the second distance.

Abstract: An integrated circuit (IC) device includes one or more functional blocks spanning a lithographic seam between adjacent lithographic fields. A functional block includes multiple instances of a pattern, each instance corresponding to a different placement option for the functional block. The IC device may include multiple such functional blocks spanning lithographic fields. The lithographic seam (and the patterns otherwise located) may include lithographic assist features, such as registration marks and metrology structures. The multiple lithographic fields may be or include high numerical aperture extreme ultraviolet lithographic fields. The lithographic seam may interface with wafer finishing collaterals (such as guard rings).

Abstract: An IC device may include functional regions as well as replica cells and filler cells that can reduce local layout effect in the IC device. A functional region includes functional cells, e.g., logic cell or memory cells. A white space may be between a first functional region and a second functional region. A first portion of the white space may be filled with replica cells, each of which is a replica of a cell in the first functional region. A second portion of the white space may be filled with filler cells that are not functional. The first function region is closer to the replica cells than to the filler cells. A third portion of the white space may be filled with replica cells, each of which is a replica of a cell in the second functional region. The second portion is between the first portion and the third portion.

Abstract: Methods, computing systems, and technology for optimizing a landing page of a website are presented. The system can receive, from a user device, a first web address associated with a first webpage of the website. The system can process, using the machine-learned assessment model, the first webpage to generate a first landing page score. The system can determine, based on the first landing page score and using a machine-learned optimization model, an actionable suggestion associated with the landing page. The system can cause, on a display of the user device, a presentation of the actionable suggestion.

Abstract: Example aspects of the present disclosure provide an example method. In some implementations, the example method can include receiving request data indicating a request for content. In some implementations, the example method can include determining a request context associated with the request data, wherein the request context is based on account data for a user device associated with the request. In some implementations, the example method can include determining, based on the request and the request context, a data object from a knowledge graph, wherein the data object comprises a subject and one or more attributes for the subject. In some implementations, the example method can include generating, using a machine-learned content generation model, content descriptive of the subject, the content generated based on the request, the request context, and the data object.

Abstract: Techniques to form an integrated circuit having a gate cut between adjacent pairs of semiconductor devices. At least one of those adjacent pairs of semiconductor devices includes a conductive link (e.g., a bridge) through the gate cut to connect the adjacent gates together. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut is present between each pair of neighboring semiconductor devices thus interrupting the gate structure and isolating the gate of one semiconductor device from the gate of the other semiconductor device. A conductive link extends over a given gate cut to electrically connect the adjacent gate electrodes together. A dielectric layer extends over the bridged gate electrodes and the conductive link, and may have different thicknesses over those respective features.

Abstract: Techniques to form an integrated circuit having a bridging contact structure. A bridging contact structure may, for example, bridge between source/drain contacts and to an adjacent gate electrode within the same device layer. In an example, a gate cut structure extends in a first direction to separate the source or drain regions and gate structures of neighboring semiconductor devices. Contacts may be formed over the source or drain regions of the neighboring devices on opposite sides of the gate cut along a second direction orthogonal to the first direction. A portion of the gate cut is replaced with a first conductive bridge between the source or drain contacts. A portion of one or more dielectric barriers between one of the source or drain contacts and an adjacent gate electrode is replaced with a second conductive bridge in the first direction between the source or drain contact and the gate structure.

Abstract: Integrated circuit structures having gate cut plugs removed from trench contacts, and methods of fabricating integrated circuit structures having gate cut plugs removed from trench contacts, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A gate cut plug extends through the gate electrode and the dielectric sidewall spacer. The gate cut plug extends into but not entirely through the conductive trench contact.

Abstract: Integrated circuit structures having uniform grid metal gate and trench contact cut, and methods of fabricating integrated circuit structures having uniform grid metal gate and trench contact cut, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to filling in whitespace between one or more groups of functional circuits on a wafer. The whitespace may be divided into a plurality of cells including periphery cells and central cells, where a portion of the cells may have the same design, where a characteristic of the plurality of cells, for example a density of metal within the cell, may be designed in order to facilitate the fabrication process of the wafer. Other embodiments may be described and/or claimed.

Abstract: Dummy gate patterning lines, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a first gate line along a first direction. A second gate line is parallel with the first gate line along the first direction. A third gate line extends between and is continuous with the first gate line and the second gate line along a second direction, the second direction orthogonal to the first direction.