Patents by Inventor Nidhir Kumar
Nidhir Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240363153Abstract: A method includes training a timing flip-flop circuit positioned between a controller and a memory resource, providing a plurality of data signals and a plurality of clock signals to the timing flip-flop circuit to generate a plurality of output clock signals and a plurality of output data signals, serializing the plurality of output clock signals and the plurality of output data signals, and providing the serialized plurality of output clock signals and the serialized plurality of output data signals to one of the controllers or the memory resources.Type: ApplicationFiled: April 18, 2024Publication date: October 31, 2024Inventors: Gyan Prakash, Nidhir Kumar, Sandeep Dwivedi
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Patent number: 10775836Abstract: A method and system for cycle accurate data transfer between skewed source synchronous clocks is envisaged. The procedure starts through reset. On reset, both the write and read address registers are set to point to location 0. Source clock is stopped to disable active clock edges to both write and read address registers during the reset procedure. The source clock is subsequently started to deliver active edges w both write and read address registers. On every active source clock edge, data is pushed into the data register based on the location pointed by write address resister. On every skewed active clock edge, data is read from the data register based on the address pointed by read address register. Due to the delayed nature of clock reaching the read address register, write address register increments first and stores data into the data register.Type: GrantFiled: June 14, 2016Date of Patent: September 15, 2020Assignee: Synopsys, Inc.Inventors: Gyan Prakash, Nidhir Kumar
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Patent number: 10725681Abstract: A method for automatic calibration of read latency of a memory module is envisaged. The read latency is initially set to a default maximum value. The default maximum value is equivalent to the number of clock cycles required to complete a data read operation. A data pattern to be read from the memory module in consideration of the default maximum value is identified. A memory read operation is preformed, and a first data pattern is captured, in accordance with the default maximum value. The identified data pattern is compared with the first data pattern, and the default maximum value is iteratively calibrated based on the comparison thereof. Aforementioned steps are repeated across a plurality of memory read operations, and variations ire the maximum default value are tracked, and an average maximum value is calculated based thereupon. The average maximum value is assigned as the read latency for the memory module.Type: GrantFiled: June 13, 2016Date of Patent: July 28, 2020Assignee: Synopsys, Inc.Inventors: Gyan Prakash, Nidhir Kumar, Chandrashekar Narla, Praphul Malige
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Patent number: 10504569Abstract: A system and method for aligning clock signals in a DDR DRAM module is disclosed. The system includes a phase detector circuitry, a controllable delay circuit, a first delay circuit and a synchronizing circuit. A clock signal is simultaneously transmitted through the first delay circuit and the controllable delay circuit. Subsequently, the clock signals transmitted through the first delay circuit and the controllable delay circuit are captured at the output thereof, and fed as inputs to the phase detector circuitry. The phase detector circuitry determines whether the clock signals are in phase, and accordingly adjusts the delay associated with the controllable delay circuit until the two clock signals are determined to be in phase.Type: GrantFiled: June 30, 2016Date of Patent: December 10, 2019Assignee: INVECAS TECHNOLOGIES PVT. LTDInventors: Gyan Prakash, Nidhir Kumar, Muniswara Reddy Vorugu
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Patent number: 10312886Abstract: The present disclosure envisages an asynchronous clock gating circuitry and a method for designing the asynchronous clock gating circuitry. The asynchronous clock gating circuitry could be placed at the very beginning of the clock network, given its design and implementation logic. The asynchronous clock gating circuitry helps meet the timing requirement on the enable pin thereof. The asynchronous clock gating circuitry avoids cumbersome replication of cluck gating circuitry during physical implementation of the (circuit) design, and further helps reduce the power consumption levels in sequential circuits.Type: GrantFiled: June 14, 2016Date of Patent: June 4, 2019Assignee: INVECAS TECHNOLOGIES PVT. LTDInventors: Gyan Prakash, Nidhir Kumar
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Patent number: 10297310Abstract: A method and system for multi cycle write leveling are disclosed. At least three data patterns are written into consecutive address locations of a memory device via corresponding write operations. Subsequently, predetermined beats of data strobe signals corresponding to certain predetermined write operations are gated. Based at least on the gating of predetermined data beats, a target data pattern to be read from the memory device is determined. Subsequently, a data read operation is performed, and the data written onto a specific address location of the memory device is read there from. The data thus read from the memory device is compared with the target pattern. Based on the comparison of the data read from the memory device with the target pattern, a delay cycle between the data strobe signals and clock signal is determined, and the data strobe signal and clock signal are accordingly calibrated.Type: GrantFiled: February 24, 2016Date of Patent: May 21, 2019Assignee: INVECAS TECHNOLOGIES PVT. LTDInventors: Gyan Prakash, Nidhir Kumar
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Publication number: 20190066740Abstract: A system and method for aligning clock signals in a DDR DRAM module is disclosed. The system includes a phase detector circuitry, a controllable delay circuit, a first delay circuit and a synchronizing circuit. A clock signal is simultaneously transmitted through the first delay circuit and the controllable delay circuit. Subsequently, the clock signals transmitted through the first delay circuit and the controllable delay circuit are captured at the output thereof, and fed as inputs to the phase detector circuitry. The phase detector circuitry determines whether the clock signals are in phase, and accordingly adjusts the delay associated with the controllable delay circuit until the two clock signals are determined to be in phase.Type: ApplicationFiled: June 30, 2016Publication date: February 28, 2019Applicant: INVECAS TECHNOLOGIES PVT. LTD.Inventors: GYAN PRAKASH, NIDHIR KUMAR, MUNISWARA REDDY VORUGU
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Publication number: 20190004564Abstract: A method and system for cycle accurate data transfer between skewed source synchronous clocks is envisaged. The procedure starts through reset. On reset, both the write and read address registers are set to point to location 0. Source clock is stopped to disable active clock edges to both write and read address registers during the reset procedure. The source clock is subsequently started to deliver active edges w both write and read address registers. On every active source clock edge, data is pushed into the data register based on the location pointed by write address resister. On every skewed active clock edge, data is read from the data register based on the address pointed by read address register. Due to the delayed nature of clock reaching the read address register, write address register increments first and stores data into the data register.Type: ApplicationFiled: June 14, 2016Publication date: January 3, 2019Inventors: GYAN PRAKASH, NIDHIR KUMAR
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Publication number: 20180357002Abstract: A method for automatic calibration of read latency of a memory module is envisaged. The read latency is initially set to a default maximum value. The default maximum value is equivalent to the number of clock cycles required to complete a data read operation. A data pattern to be read from the memory module in consideration of the default maximum value is identified. A memory read operation is preformed, and a first data pattern is captured, in accordance with the default maximum value. The identified data pattern is compared with the first data pattern, and the default maximum value is iteratively calibrated based on the comparison thereof. Aforementioned steps are repeated across a plurality of memory read operations, and variations ire the maximum default value are tracked, and an average maximum value is calculated based thereupon. The average maximum value is assigned as the read latency for the memory module.Type: ApplicationFiled: June 13, 2016Publication date: December 13, 2018Inventors: GYAN PRAKASH, NIDHIR KUMAR, CHANDRASHEKAR NARLA
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Publication number: 20180351537Abstract: The present disclosure envisages an asynchronous clock gating circuitry and a method for designing the asynchronous clock gating circuitry. The asynchronous clock gating circuitry could be placed at the very beginning of the clock network, given its design and implementation logic. The asynchronous clock gating circuitry helps meet the timing requirement on the enable pin thereof. The asynchronous clock gating circuitry avoids cumbersome replication of cluck gating circuitry during physical implementation of the (circuit) design, and further helps reduce the power consumption levels in sequential circuits.Type: ApplicationFiled: June 14, 2016Publication date: December 6, 2018Inventors: GYAN PRAKASH, NIDHIR KUMAR
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Publication number: 20180075898Abstract: A method and system for multi cycle write leveling are disclosed. At least three data patterns are written into consecutive address locations of a memory device via corresponding write operations. Subsequently, predetermined beats of data strobe signals corresponding to certain predetermined write operations are gated. Based at least on the gating of predetermined data beats, a target data pattern to be read from the memory device is determined. Subsequently, a data read operation is performed, and the data written onto a specific address location of the memory device is read there from. The data thus read from the memory device is compared with the target pattern. Based on the comparison of the data read from the memory device with the target pattern, a delay cycle between the data strobe signals and clock signal is determined, and the data strobe signal and clock signal are accordingly calibrated.Type: ApplicationFiled: February 24, 2016Publication date: March 15, 2018Inventors: GYAN PRAKASH, NIDHIR KUMAR
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Patent number: 9213359Abstract: Interface circuitry transmitting transactions between an initiator and a recipient includes: a clock input receiving a clock signal; a transaction input receiving transactions; clock outputs for outputting the clock signal; transaction outputs outputting the transactions to the recipient; and synchronizing circuits clocked by the clock signal and transmitting the transactions to the transaction output in response to the clock signal. A controllable delay circuit is provided between the clock input and the synchronizing circuits. A further synchronizing circuit configured to provide a similar delay. Phase detection circuitry is arranged to detect alignment of the received clock signals. Calibration control circuitry adjusts a delay of the controllable delay circuit during calibration until the phase detection circuitry detects alignment.Type: GrantFiled: December 24, 2012Date of Patent: December 15, 2015Assignee: ARM LimitedInventors: Gyan Prakash, Nidhir Kumar
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Patent number: 9105327Abstract: A memory controller and a method of calibrating the memory controller are provided. Input circuitry in the memory controller receives a differential pair of data strobe signals from a memory and generates a logical data strobe signal in dependence on a voltage difference between the differential pair of data strobe signals. Hysteresis circuitry, when active, increases by a predetermined offset a threshold voltage difference at which the input circuitry changes a logical state of the logical data strobe signal. Gate signal generation circuitry generates a data strobe gating signal, wherein the memory controller interprets the logical data strobe signal as valid when the data strobe gating signal is asserted.Type: GrantFiled: April 12, 2013Date of Patent: August 11, 2015Assignee: ARM LimitedInventors: Gyan Prakash, Ranabir Dey, Nidhir Kumar
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Patent number: 9042188Abstract: A memory controller transmits a data signal, a data strobe signal and a mask signal to a memory, wherein each transition of the data strobe signal indicates a sample point for the data signal and the mask signal indicates a validity of the data signal. A mask signal training procedure is carried out comprising three steps. Writing first and second values to the memory for a predetermined plurality of transitions of the data strobe signal with the mask signal set to indicate that the first data signal is valid and the second data signal is valid except for a selected transition of the predetermined plurality. Reading from the memory for the predetermined plurality of transitions of the data strobe signal. Determining a timing offset for the mask signal for which the value read at the selected transition matches the first value.Type: GrantFiled: April 1, 2013Date of Patent: May 26, 2015Assignee: ARM LimitedInventors: Gyan Prakash, Nidhir Kumar
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Patent number: 9007855Abstract: A method of calibrating a data signal receiver configured to receive a multi-bit data signal and an associated data strobe signal, wherein transitions of the data strobe signal indicate sample points for the multi-bit data signal.Type: GrantFiled: December 24, 2012Date of Patent: April 14, 2015Assignee: ARM LimitedInventors: Nidhir Kumar, Gyan Prakash, Muniswara Reddy Vorugu
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Patent number: 8780655Abstract: A method of aligning a clock signal and a data strobe signal in a system comprising a memory controller and a memory, and a corresponding memory system are provided.Type: GrantFiled: December 24, 2012Date of Patent: July 15, 2014Assignee: ARM LimitedInventors: Nidhir Kumar, Gyan Prakash, Chandrashekar Narla
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Patent number: 8773185Abstract: A calibratable delay chain having a delay chain and an adjustment circuitry varying a delay of each of the plurality of delay stages in the chain. The calibration circuitry is configured to calibrate a delay of the delay chain. The calibration circuitry includes calibration control circuitry for controlling the calibration and supplying the input value to an adjustment circuitry. Output selection circuitry is provided to select an output from a predetermined point along the delay chain. A bypass path bypasses the delay chain and a digital comparator compares an output from the delay chain and an output from the bypass path. An analogue comparator compares an output from the delay chain and an output from the bypass path. The calibration control circuitry is configured to control the output selection circuitry to output a signal from one point on the delay chain to the digital comparator.Type: GrantFiled: November 20, 2012Date of Patent: July 8, 2014Assignee: ARM LimitedInventors: Sivaramakrishnan Subramanian, Nidhir Kumar, Sridhar Cheruku
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Publication number: 20140181568Abstract: Interface circuitry transmitting transactions between an initiator and a recipient includes: a clock input receiving a clock signal; a transaction input receiving transactions; clock outputs for outputting the clock signal; transaction outputs outputting the transactions to the recipient; and synchronising circuits clocked by the clock signal and transmitting the transactions to the transaction output in response to the clock signal. A controllable delay circuit is provided between the clock input and the synchronising circuits. A further synchronising circuit configured to provide a similar delay. Phase detection circuitry is arranged to detect alignment of the received clock signals. Calibration control circuitry adjusts a delay of the controllable delay circuit during calibration until the phase detection circuitry detects alignment.Type: ApplicationFiled: December 24, 2012Publication date: June 26, 2014Applicant: ARM LimitedInventors: Gyan Prakash, Nidhir Kumar
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Publication number: 20140177377Abstract: A method of calibrating a data signal receiver configured to receive a multi-bit data signal and an associated data strobe signal, wherein transitions of the data strobe signal indicate sample points for the multi-bit data signal.Type: ApplicationFiled: December 24, 2012Publication date: June 26, 2014Applicant: ARM LimitedInventors: Nidhir KUMAR, Gyan PRAKASH, Munisware Reddy VORUGU
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Publication number: 20140177359Abstract: A method of aligning a clock signal and a data strobe signal in a system comprising a memory controller and a memory, and a corresponding memory system are provided.Type: ApplicationFiled: December 24, 2012Publication date: June 26, 2014Applicant: ARM LimitedInventors: Nidhir KUMAR, Gyan PRAKASH, Chandrashekar NARLA