Abstract: A rocket landing stabilization system can include one or more upright support structures such as posts, columns, or walls, from which one or more stabilizing elements can be supported. The stabilizing elements can be used to stabilize a rocket as it lands at a landing site. The rocket landing stabilization system can also include a cradle, funnel, or cone to catch or otherwise support a rocket as it lands at the landing site. The rocket landing stabilization system can be located on land or at sea.

Abstract: A rocket landing stabilization system can include one or more upright support structures such as posts, columns, or walls, from which one or more stabilizing elements can be supported. The stabilizing elements can be used to stabilize a rocket as it lands at a landing site. The rocket landing stabilization system can also include a cradle, funnel, or cone to catch or otherwise support a rocket as it lands at the landing site. The rocket landing stabilization system can be located on land or at sea.

Abstract: A rocket landing stabilization system can include one or more upright support structures such as posts, columns, or walls, from which one or more stabilizing elements can be supported. The stabilizing elements can be used to stabilize a rocket as it lands at a landing site. The rocket landing stabilization system can also include a cradle, funnel, or cone to catch or otherwise support a rocket as it lands at the landing site. The rocket landing stabilization system can be located on land or at sea.

Abstract: A rocket landing stabilization system can include one or more upright support structures such as posts, columns, or walls, from which one or more stabilizing elements can be supported. The stabilizing elements can be used to stabilize a rocket as it lands at a landing site. The rocket landing stabilization system can also include a cradle, funnel, or cone to catch or otherwise support a rocket as it lands at the landing site. The rocket landing stabilization system can be located on land or at sea.

Abstract: A rocket landing stabilization system can include one or more upright support structures such as posts, columns, or walls, from which one or more stabilizing elements can be supported. The stabilizing elements can be used to stabilize a rocket as it lands at a landing site. The rocket landing stabilization system can also include a cradle, funnel, or cone to catch or otherwise support a rocket as it lands at the landing site. The rocket landing stabilization system can be located on land or at sea.

Abstract: A rocket landing stabilization system can include one or more upright support structures such as posts, columns, or walls, from which one or more stabilizing elements can be supported. The stabilizing elements can be used to stabilize a rocket as it lands at a landing site. The rocket landing stabilization system can also include a cradle, funnel, or cone to catch or otherwise support a rocket as it lands at the landing site. The rocket landing stabilization system can be located on land or at sea.

Abstract: A rocket landing stabilization system can include one or more upright support structures such as posts, columns, or walls, from which one or more stabilizing elements can be supported. The stabilizing elements can be used to stabilize a rocket as it lands at a landing site. The rocket landing stabilization system can also include a cradle, funnel, or cone to catch or otherwise support a rocket as it lands at the landing site. The rocket landing stabilization system can be located on land or at sea.

Abstract: A rocket landing stabilization system can include one or more upright support structures such as posts, columns, or walls, from which one or more stabilizing elements can be supported. The stabilizing elements can be used to stabilize a rocket as it lands at a landing site. The rocket landing stabilization system can also include a cradle, funnel, or cone to catch or otherwise support a rocket as it lands at the landing site. The rocket landing stabilization system can be located on land or at sea.

Abstract: A rocket landing stabilization system can include one or more upright support structures such as posts, columns, or walls, from which one or more stabilizing elements can be supported. The stabilizing elements can be used to stabilize a rocket as it lands at a landing site. The rocket landing stabilization system can also include a cradle, funnel, or cone to catch or otherwise support a rocket as it lands at the landing site. The rocket landing stabilization system can be located on land or at sea.

Abstract: A rocket landing stabilization system can include one or more upright support structures such as posts, columns, or walls, from which one or more stabilizing elements can be supported. The stabilizing elements can be used to stabilize a rocket as it lands at a landing site. The rocket landing stabilization system can also include a cradle, funnel, or cone to catch or otherwise support a rocket as it lands at the landing site. The rocket landing stabilization system can be located on land or at sea.

Abstract: A Sampled Pipeline Subranging Converter (SPSC) may include at least one stage—e.g. at least the input stage—operating in a time-continuous fashion. In the time continuous input stage, the analog input may be processed in two parallel paths. A lower path may comprise a track-and-hold (T/H) element, an Analog-to-Digital-Converter (ADC) and a Digital-to-Analog-Converter (DAC). The T/H element may be optional and may be present if required by the ADC. The signal entering the lower path may be sampled at the desired conversion rate. The time continuous stage(s) may additionally be configured with an upper path that includes a delay element configured to receive the analog input, a Low-Pass (LP) filter coupled to the delay element, and an anti alias filter. The output generated by the DAC may be subtracted from the output of the LP filter, and the resulting difference signal may be provided to the anti alias filter, which in turn may generate the residue (or error) output.

Abstract: A Sampled Pipeline Subranging Converter (SPSC) may include at least one stage—e.g. at least the input stage—operating in a time-continuous fashion. In the time continuous input stage, the analog input may be processed in two parallel paths. A lower path may comprise a track-and-hold (T/H) element, an Analog-to-Digital-Converter (ADC) and a Digital-to-Analog-Converter (DAC). The T/H element may be optional and may be present if required by the ADC. The signal entering the lower path may be sampled at the desired conversion rate. The time continuous stage(s) may additionally be configured with an upper path that includes a delay element configured to receive the analog input, a Low-Pass (LP) filter coupled to the delay element, and an anti alias filter. The output generated by the DAC may be subtracted from the output of the LP filter, and the resulting difference signal may be provided to the anti alias filter, which in turn may generate the residue (or error) output.

Abstract: A system and method for accurately detecting an asynchronous frequency within a synchronous digital system. The improved system and method preconditions the asynchronous frequency so that it does not introduce additional phase noise at low frequencies within a digital PLL. The system comprises a digitally controlled oscillator, having a preconditioner and a digital phase locked loop. The preconditioner receives an input clock signal and outputs a modified clock signal that is synchronized to a master clock signal. The digital phase locked loop receives the modified clock signal output from the preconditioner and outputs an output clock signal that is a version of the input clock signal synchronized to the master clock signal. The preconditioner preferably has a higher bandwidth than the digital PLL, and the preconditioner operates to noise shape phase noise of the synchronization to higher frequencies. The digital phase locked loop may then operate to remove the phase noise at the higher frequencies.

Abstract: A system and method for calibrating an analog to digital (A/D) converter. The A/D converter includes an internal D/A converter, wherein the internal D/A converter includes a plurality of current generators, and wherein one or more of the current generators may produce linearity errors in the A/D converter. The A/D converter includes a switching element connected to the internal D/A converter. During calibration, the switching element operates to adjust connections to the current generators in the internal D/A converter one or more times according to different switching patterns, thereby causing different ones of the current generators to be stimulated by an input to the A/D converter. This avoids the necessity of using a complex and costly waveform generator input during calibration, which would normally be required to ensure that all of the current generators in the internal D/A converter are stimulated. Rather, a much simpler input can be used in calibrating the A/D converter, thereby reducing cost.

Abstract: A system and method for accurately detecting an asynchronous frequency within a synchronous digital system. The improved system and method preconditions the asynchronous frequency so that it does not introduce additional phase noise at low frequencies within a digital PLL. The system comprises a digitally controlled oscillator, having a preconditioner and a digital phase locked loop. The preconditioner receives an input clock signal and outputs a modified clock signal that is synchronized to a master clock signal. The digital phase locked loop receives the modified clock signal output from the preconditioner and outputs an output clock signal that is a version of the input clock signal synchronized to the master clock signal. The preconditioner preferably has a higher bandwidth than the digital PLL, and the preconditioner operates to noise shape phase noise of the synchronization to higher frequencies. The digital phase locked loop may then operate to remove the phase noise at the higher frequencies.

Abstract: A system and method for calibrating an analog to digital (A/D) converter. The A/D converter includes an internal D/A converter, wherein the internal D/A converter includes a plurality of current generators, and wherein one or more of the current generators may produce linearity errors in the A/D converter. The A/D converter includes a switching element connected to the internal D/A converter. During calibration, the switching element operates to adjust connections to the current generators in the internal D/A converter one or more times according to different switching patterns, thereby causing different ones of the current generators to be stimulated by an input to the A/D converter. This avoids the necessity of using a complex and costly waveform generator input during calibration, which would normally be required to ensure that all of the current generators in the internal D/A converter are stimulated. Rather, a much simpler input can be used in calibrating the A/D converter, thereby reducing cost.

Abstract: A flash A/D conversion system and method with a reduced number of comparators. The voltage range applied by the comparators is moved or adjusted to provide an A/D converter with a much greater voltage range. The system comprises a reduced plurality of comparators each coupled to receive an analog input signal, and a decoder coupled to receive the outputs of the comparators. Each comparator also receives a respective comparator reference signal for comparison with the analog input signal, and outputs a digital value indicative of the comparison between the analog input signal and the respective comparator reference signal. In one embodiment, a dynamic reference controller dynamically outputs one or more dynamic reference voltages to the plurality of comparators, wherein the comparators may receive different comparator reference voltages for comparing with the analog input signal.

Abstract: An analog to digital (A/D) converter which includes A/D converter and D/A converter modes. The A/D converter includes an internal digital to analog (D/A) converter (DAC) that may be used in a feedback loop during A/D operations (in the A/D mode), and may be used as a stand-alone D/A converter in the D/A mode. The present invention also takes advantage of advanced calibration techniques available for the internal D/A converter of the A/D converter. A processing unit may be coupled to the output of the internal A/D converter. The processing unit or a separate computer system may perform a calibration function in the A/D mode to generate linearity error correction information for correcting linearity errors in the internal D/A converter. The linearity error correction information may be used in configuring a linearity error correction device implemented by the processing unit. In the A/D mode, the processing unit may implement linearity error correction and a decimation function during A/D conversion.

Abstract: Analog-to-digital conversion with reduce sparkle codes. An analog-to-digital converter includes a plurality of comparators each coupled to receive an analog input signal, and an adder decoder coupled to receive the outputs of the comparators. Each comparator also receives a respective reference signal for comparison with the analog input signal. Each comparator outputs a digital value indicative of the comparison between the analog input signal and the respective reference signal. The adder decoder adds the digital output signals generated by the comparators and outputs a digital representation of the analog input signal based on the result. This system may advantageously provide for a more efficient way to convert analog signals to digital signals without the generation of sparkle codes. The adder decoder may be a pyramid of adders. A sigma-delta converter may include the comparators in the analog-to-digital portion in the feedback loop and the adder decoder outside of the feedback loop.

Abstract: A system and method for reducing linearity errors in an A/D converter, such as a delta-sigma converter. The linearity errors in the delta-sigma converter are modeled by generating a set of digital signals representative of an inputted sine wave. The set of digital signals are low-pass filtered and subjected to a fast Fourier transform algorithm to generate a frequency domain representation of the sine wave. Thereafter, a net linearity error spectrum is removed from the frequency domain representation and inverse Fourier transform back into the time domain. The filtered set of digital signals are also sorted into subsets of digital signals where each signal in a subset corresponds to a particular output of a delta-sigma modulator contained within the delta-sigma converter. A fast Fourier transform algorithm is applied to each of the filtered subsets of digital signals to generate a frequency domain representation thereof.