Abstract: A method includes providing a semiconductor structure including: a substrate; a layer stack with each layer of the layer stack including a Group III-nitride material; and a p-type doped GaN layer on the layer stack. The method also includes providing, on the GaN layer, a metal bi-layer including a first metal layer in contact with GaN layer and a second metal layer on the first metal layer and having a lower sheet resistance than the first metal layer. The method also includes performing a patterning process upon the metal bi-layer and the p-type doped GaN layer such that a first periphery of the first metal layer is aligned to a second periphery of the second metal layer and such that a first cross section of the metal bi-layer is smaller than a second cross section of the GaN layer parallel to the first cross section.

Abstract: A method includes providing a semiconductor structure including: a substrate; a layer stack with each layer of the layer stack including a Group III-nitride material; and a p-type doped GaN layer on the layer stack. The method also includes providing, on the GaN layer, a metal bi-layer including a first metal layer in contact with GaN layer and a second metal layer on the first metal layer and having a lower sheet resistance than the first metal layer. The method also includes performing a patterning process upon the metal bi-layer and the p-type doped GaN layer such that a first periphery of the first metal layer is aligned to a second periphery of the second metal layer and such that a first cross section of the metal bi-layer is smaller than a second cross section of the GaN layer parallel to the first cross section.

Abstract: Example embodiments relate to enhancement-mode high electron mobility transistors. One embodiment includes a method for manufacturing an enhancement-mode high electron mobility transistor. The method includes providing a stack of layers. The stack of layers includes a substrate, a III-V channel layer over the substrate, a III-V barrier layer on the channel layer, a p-doped III-V layer on the III-V barrier layer, and a Schottky contact interlayer on the p-doped III-V layer. The p-doped III-V layer has a first surface area. The Schottky contact interlayer has a second surface area. The second surface area is less than the first surface area. The second surface area leaves a peripheral part of a top surface of the p-doped III-V layer uncovered. The method also includes depositing a metal gate on the Schottky contact interlayer.

Abstract: Example embodiments relate to enhancement-mode high electron mobility transistors. One embodiment includes a method for manufacturing an enhancement-mode high electron mobility transistor. The method includes providing a stack of layers. The stack of layers includes a substrate, a III-V channel layer over the substrate, a III-V barrier layer on the channel layer, a p-doped III-V layer on the III-V barrier layer, and a Schottky contact interlayer on the p-doped III-V layer. The p-doped III-V layer has a first surface area. The Schottky contact interlayer has a second surface area. The second surface area is less than the first surface area. The second surface area leaves a peripheral part of a top surface of the p-doped III-V layer uncovered. The method also includes depositing a metal gate on the Schottky contact interlayer.

Abstract: The disclosure relates to a method of fabricating an enhancement mode Group III-nitride HEMT device and a Group III-nitride structure fabricated therefrom. One example embodiment is a method for fabricating an enhancement mode Group III-nitride HEMT device. The method includes providing a structure. The structure includes a substrate having a main surface. The structure also includes a layer stack overlying the main surface. Each layer of the layer stack includes a Group III-nitride material. The structure further includes a capping layer on the layer stack. The method also includes forming a recessed gate region by removing, in a gate region, at least the capping layer by performing an etch process, thereby exposing a top surface of an upper layer of the layer stack. The method further includes forming a p-type doped GaN layer in the recessed gate region and on the capping layer by performing a non-selective deposition process.

Abstract: The disclosure relates to a method of fabricating an enhancement mode Group III-nitride HEMT device and a Group III-nitride structure fabricated therefrom. One example embodiment is a method for fabricating an enhancement mode Group III-nitride HEMT device. The method includes providing a structure. The structure includes a substrate having a main surface. The structure also includes a layer stack overlying the main surface. Each layer of the layer stack includes a Group III-nitride material. The structure further includes a capping layer on the layer stack. The method also includes forming a recessed gate region by removing, in a gate region, at least the capping layer by performing an etch process, thereby exposing a top surface of an upper layer of the layer stack. The method further includes forming a p-type doped GaN layer in the recessed gate region and on the capping layer by performing a non-selective deposition process.

Abstract: The disclosed technology generally relates to forming patterns of doped semiconductor regions, and more particularly to methods of forming such patterns in fabricating photovoltaic devices. In one aspect, a method of forming a pattern of different doped regions at the same side of a semiconductor substrate comprises providing a patterned doped layer on a surface of the semiconductor substrate at predetermined locations where at least one first doped region is to be formed. The method additionally includes selectively growing at least one second doped region epitaxially at the same side of the semiconductor substrate using the patterned doped layer as an epitaxial growth mask. Furthermore, selectively growing comprises driving dopants from the patterned doped layer into the semiconductor substrate to form the first doped region at the predetermined locations.

Abstract: An integrated circuit comprising a first III-N transistor having a source region and a second III-N transistor having a source region, both transistors being monolithically integrated on a common silicon substrate of a first doping type and separated from each-other by an isolation region, the substrate comprising underneath the first transistor a well of a first doping type electrically connected to the source region of the first transistor and comprising underneath the second transistor a well of a second doping type electrically connected to the source region of the second transistor, thereby forming a junction diode in the substrate between the sources of the first and the second transistor.

Abstract: The disclosed technology generally relates to forming patterns of doped semiconductor regions, and more particularly to methods of forming such patterns in fabricating photovoltaic devices. In one aspect, a method of forming a pattern of different doped regions at the same side of a semiconductor substrate comprises providing a patterned doped layer on a surface of the semiconductor substrate at predetermined locations where at least one first doped region is to be formed. The method additionally includes selectively growing at least one second doped region epitaxially at the same side of the semiconductor substrate using the patterned doped layer as an epitaxial growth mask. Furthermore, selectively growing comprises driving dopants from the patterned doped layer into the semiconductor substrate to form the first doped region at the predetermined locations.

Abstract: A method is disclosed for passivating and contacting a surface of a germanium substrate. A passivation layer of amorphous silicon material is formed on the germanium surface. A contact layer of metal, e.g., aluminum, is then formed on the passivation layer. The structure is heated so that the germanium surface makes contact with the contact layer. The aluminum contact layer can be configured for use as a mirroring surface for the back surface of the device. Thus, a passivated germanium surface is disclosed, as well as a solar cell comprising such a structure.

Abstract: A method is disclosed for passivating and contacting a surface of a germanium substrate. A passivation layer of amorphous silicon material is formed on the germanium surface. A contact layer of metal is then formed on the passivation. The structure is heated so that the germanium surface makes contact with the contact layer. Thus, a passivated germanium surface is disclosed, as well as a solar cell comprising such a structure.

Abstract: A method is disclosed for passivating and contacting a surface of a germanium substrate. A passivation layer of amorphous silicon material is formed on the germanium surface. A contact layer of metal is then formed on the passivation. The structure is heated so that the germanium surface makes contact with the contact layer. Thus, a passivated germanium surface is disclosed, as well as a solar cell comprising such a structure.

Abstract: A method is disclosed for passivating and contacting a surface of a germanium substrate. A passivation layer of amorphous silicon material is formed on the germanium surface. A contact layer of metal is then formed on the passivation. The structure is heated so that the germanium surface makes contact with the contact layer. Thus, a passivated germanium surface is disclosed, as well as a solar cell comprising such a structure.

Abstract: A method is disclosed for passivating and contacting a surface of a germanium substrate. A passivation layer of amorphous silicon material is formed on the germanium surface. A contact layer of metal, e.g., aluminum, is then formed on the passivation layer. The structure is heated so that the germanium surface makes contact with the contact layer. The aluminum contact layer can be configured for use as a mirroring surface for the back surface of the device. Thus, a passivated germanium surface is disclosed, as well as a solar cell comprising such a structure.

Abstract: A method is disclosed for passivating and contacting a surface of a germanium substrate. A passivation layer of amorphous silicon material is formed on the germanium surface. A contact layer of metal is then formed on the passivation. The structure is heated so that the germanium surface makes contact with the contact layer. Thus, a passivated germanium surface is disclosed, as well as a solar cell comprising such a structure.