Abstract: A method and circuit are described for ensuring a properly operational power-up read of fuse cells in a nonvolatile memory by selecting predefined data for loading in a portion of a fuse memory and matching the reading of the predefined data during power-up with the predefined data, thereby indicating a proper power-up read of fuse cells. The fuse memory is partitioned into a first section of fuse cells for conducting a pre-check procedure to match a first predefined data being read against the first predefined data, a second section for reading main fuse cells to match with a second predefined data being read against the second predefined data, and a third section of fuse cells for conducting a post-check procedure to match a third predefined data being read against the third predefined data.

Abstract: The present invention provides a read-only memory array having a flat-type structure. The read-only memory array comprises at least two memory banks having a plurality of memory cells. At least two inter-bank transistors are coupled to the two memory banks and shared by the two memory banks. Each inter-bank transistor is used for enabling to select the memory cells of the two memory banks. At least a contact commonly is coupled to the two memory banks through the two inter-bank transistors.

Abstract: A low power latch sense amplifier for electrically being coupled to a bit line of a memory cell array is disclosed. The low power latch sense amplifier comprises a common gate sense amplifier and an activated latch register. The common gate sense amplifier comprising a current source and a biased metal-oxide semiconductor is applied for sensing the current of the bit line. The current source and the biased MOS are coupled to a first node, and the common gate sense amplifier outputs a sensing signal at the first node. The activated latch register comprises a first clock signal-synchronized inverter which includes a first inverter and a first switch. The first inverter responds to the sensing signal, and the first inverter outputs a first inverter output signal. The first switch is controlled by a first set of control signal, and the first inverter output signal is corresponding to the sensing signal when the first switch is turned on.

Abstract: A sense amplifier inverts the output from the pass transistor to control a pre-charge transistor. The combination of the inverter and pre-charge transistor pre-charges the output to a level just below the flip level of the following data latch circuit. If the data cell read is a low threshold cell (conductive or “1”), the output level does not significantly change, and the data is rapidly latched and read. If the data cell is a high threshold cell (non-conductive or “0”), the pass transistor shuts off and the output is pulled up above the flip level of the data latch circuit through a pull-up path. The pre-charge level is near the flip level, so the output does not have to be pulled up very far, thus reading a “0” is also fast. In one embodiment, the pull-up transistor is a p-channel MOSFET with the gate grounded, thus providing more constant current than a diode-connected configuration.

Abstract: The present invention provides a read-only memory array having a flat-type structure. The read-only memory array comprises at least two memory banks having a plurality of memory cells. At least two inter-bank transistors are coupled to the two memory banks and shared by the two memory banks. Each inter-bank transistor is used for enabling to select the memory cells of the two memory banks. At least a contact commonly is coupled to the two memory banks through the two inter-bank transistors.

Abstract: A sense amplifier inverts the output from the pass transistor to control a pre-charge transistor. The combination of the inverter and pre-charge transistor pre-charges the output to a level just below the flip level of the following data latch circuit. If the data cell read is a low threshold cell (conductive or “1”), the output level does not significantly change, and the data is rapidly latched and read. If the data cell is a high threshold cell (non-conductive or “0”), the pass transistor shuts off and the output is pulled up above the flip level of the data latch circuit through a pull-up path. The pre-charge level is near the flip level, so the output does not have to be pulled up very far, thus reading a “0” is also fast. In one embodiment, the pull-up transistor is a p-channel MOSFET with the gate grounded, thus providing more constant current than a diode-connected configuration.

Abstract: A low power latch sense amplifier for electrically being coupled to a bit line of a memory cell array is disclosed. The low power latch sense amplifier comprises a source follower sense amplifier and an activated latch register. The source follower sense amplifier comprising a current source and a biased metal-oxide semiconductor is applied for sensing the current of the bit line. The current source and the biased MOS are coupled to a first node, and the source follower sense amplifier outputs a sensing signal at the first node. The activated latch register comprises a first clock signal-synchronized inverter which includes a first inverter and a first switch. The first inverter responses to the sensing signal, and the first inverter outputs a first inverter output signal. The first switch is controlled by a first set of control signal, and the first inverter output signal is corresponding to the sensing signal when the first switch is turned on.

Abstract: A flat-cell nonvolatile semiconductor memory. The semiconductor memory includes a plurality of units. Each unit includes word lines, a main bit line, a ground line, sub-bit lines, memory cell columns, and bank-selecting switches. Word lines are disposed in parallel, and the main bit line and the ground line cross the word lines. Sub-bit lines are disposed substantially in parallel to the main bit lines. Each memory cell column includes a plurality of memory cells connected in parallel between respective adjacent two of the sub-bit lines. The bank-selecting switches are used to select one of the memory cell columns. The first one of the bank-selecting switches is disposed between the main bit line and the fourth sub-bit line. The second of the bank-selecting switches is disposed between the main bit line and the second sub-bit line. The third of the bank-selecting switches is disposed between the ground line and the fifth sub-bit line.

Abstract: A sense amplifier inverts the output from the pass transistor to control a pre-charge transistor. The combination of the inverter and pre-charge transistor pre-charges the output to a level just below the flip level of the following data latch circuit. If the data cell read is a low threshold cell (conductive or “1”), the output level does not significantly change, and the data is rapidly latched and read. If the data cell is a high threshold cell (non-conductive or “0”), the pass transistor shuts off and the output is pulled up above the flip level of the data latch circuit through a pull-up path. The pre-charge level is near the flip level, so the output does not have to be pulled up very far, thus reading a “0” is also fast. In one embodiment, the pull-up transistor is a p-channel MOSFET with the gate grounded, thus providing more constant current than a diode-connected configuration.

Abstract: The present invention provides a read-only memory array having a flat-type structure. The read-only memory array comprises at least two memory banks having a plurality of memory cells. At least two inter-bank transistors are coupled to the two memory banks and shared by the two memory banks. Each inter-bank transistor is used for enabling to select the memory cells of the two memory banks. At least a contact commonly is coupled to the two memory banks through the two inter-bank transistors.

Abstract: A sense amplifier inverts the output from the pass transistor to control a pre-charge transistor. The combination of the inverter and pre-charge transistor pre-charges the output to a level just below the flip level of the following data latch circuit. If the data cell read is a low threshold cell (conductive or “1”), the output level does not significantly change, and the data is rapidly latched and read. If the data cell is a high threshold cell (non-conductive or “0”), the pass transistor shuts off and the output is pulled up above the flip level of the data latch circuit through a pull-up path. The pre-charge level is near the flip level, so the output does not have to be pulled up very far, thus reading a “0” is also fast. In one embodiment, the pull-up transistor is a p-channel MOSFET with the gate grounded, thus providing more constant current than a diode-connected configuration.

Abstract: An integrated circuit memory comprises an array of non-volatile memory cells arranged in rows and columns, and including a plurality of banks. There are a plurality of word lines along the plurality of rows in the array, and a plurality of array bit lines arranged along the plurality of columns. The array bit lines extend across the array, and include sense lines and ground lines. A plurality of bank bit lines is arranged along the plurality of columns. The bank bit lines extend across corresponding banks in the plurality of banks and are coupled to memory cells in the corresponding banks. A plurality of connection terminals are coupled to the array bit lines. For each array bit line there is at least one connection terminal per bank in the plurality of banks for which the array bit line will be used. A plurality of bank select transistors is provided to act as bank select circuitry.

Abstract: A reading circuit for a multibit memory cell in a memory array, the memory cell having a threshold gate voltage within a range of one of a first, second, third and fourth predetermined threshold voltages corresponding respectively to one of four states of two bits stored in the memory cell. The reading circuit includes a circuit to provide a gate voltage to the multibit memory cell during a read cycle, the gate voltage having a first level between the second and third predetermined threshold voltages during a first time interval of the read cycle and a second level between the third and fourth predetermined threshold voltages during a second time interval of the read cycle.

Abstract: A reading circuit for a multibit memory cell in a memory array, the memory cell having a threshold gate voltage within a range of one of a first, second, third and fourth predetermined threshold voltages corresponding respectively to one of four states of two bits stored in the memory cell.

Abstract: A redundancy architecture suitable for high density integrated circuit memory, such as mask ROM is based on a two transistor redundancy cell that has a very small layout. Both row and column failure modes can be repaired. The memory used to characterize the failed row or column is implemented using an extra column or row respectively which is manufactured in a compact layout adjacent the array. Both an extra column and an extra row are laid out adjacent the array, using novel two transistor floating gate cells. Mode select logic is included by which replacement of a row or of a column is selected for the device. In the replacement row mode, a memory cell in the extra column is used to indicate the row to be replaced, and to enable the reading of the data from the replacement word line in place of the failed row.

Abstract: A redundancy architecture suitable for high density mask ROM integrated circuit memory is based on a two transistor redundancy cell that has a very small layout. Both row and column failure modes can be repaired. The redundancy architecture can be manufactured using typical single metal, single polysilicon mask ROM processes. Redundancy cells are based upon a diffusion word line, a redundant word line adapted to replace a word line in the array and spaced away from the diffusion word line. First and second diffusion regions between the diffusion word line and the redundant word line, and a channel region between the first diffusion region and a second diffusion region form part of the redundant cell. A third diffusion region adjacent the redundant word line opposite the second diffusion region is arranged so that the second diffusion region acts as a source terminal, the third diffusion region acts as a drain terminal, and the redundant word line acts as a gate of a transistor.

Abstract: The sense amplifier of the present invention contains a circuit that can pre-charge its output to a default state (e.g., the "0" state) during one time period and sets the output to a second state in another time period only if there is a need to do so. In this sense amplifier, cell leakage (and not cell current) is used as reference. Further, only the second state needs to be developed. As a result, the sensing margin increases. One characteristics of the present sense amplifier is that different parts of the circuit is active during different time period. As a result, both noise and power consumption is reduced. The sense amplifier is coupled to a timing circuit that can provide appropriate timing signals to operate the sense amplifier. In addition, a power-on reset circuit is disclosed. This reset circuit is operative when power is first applied to the system. It causes the timing circuit to generates a timing signal so that valid data can be detected by the sense amplifier when power is turned on.