Abstract: The disclosure relates to technology for processing images to detect LED on pulses within the images. An image processing device and method includes a fusion processor and process configured to receive the sequential long and short exposure images and output a fusion image including added corresponding regions of adjacent sequential long and short exposure images. The image processing device and method also includes an LED detection processor and method configured to receive the fusion image, a WDR image and the sequential long and short exposure images and output a control signal indicating whether each corresponding region includes an LED flicker or motion. The image processing device and method also includes a blending processor and method responsive to the control signal to generate a blended image for the sequential long and short exposure images.

Abstract: The disclosure relates to technology for processing images to detect LED on pulses within the images. An image processing device and method includes a fusion processor and process configured to receive the sequential long and short exposure images and output a fusion image including added corresponding regions of adjacent sequential long and short exposure images. The image processing device and method also includes an LED detection processor and method configured to receive the fusion image, a WDR image and the sequential long and short exposure images and output a control signal indicating whether each corresponding region includes an LED flicker or motion. The image processing device and method also includes a blending processor and method responsive to the control signal to generate a blended image for the sequential long and short exposure images.

Abstract: A hybrid architecture of a television (TV) receiving system is disclosed. The architecture includes two portions, a hardware portion and a software portion. The hardware portion includes a minimum amount of hardware to achieve operations of receiving a RF signal, producing an IF signal and outputting data representing the IP signal. The software portion, taking advantage of available computing power (e.g., high-speed microprocessor and a lot of memory) in a computing device and executed therein, includes one or more demodulators, all implemented in software. Each of the demodulators is implemented in accordance with one type of TV standard. Thus depending on the received data, a corresponding demodulator is activated to demodulate the received data and subsequently produces audio and video data.

Abstract: A hybrid architecture of a television (TV) receiving system is disclosed. The architecture includes two portions, a hardware portion and a software portion. The hardware portion includes a minimum amount of hardware to achieve operations of receiving a RF signal, producing an IF signal and outputting data representing the IP signal. The software portion, taking advantage of available computing power (e.g., high-speed microprocessor and a lot of memory) in a computing device and executed therein, includes one or more demodulators, all implemented in software. Each of the demodulators is implemented in accordance with one type of TV standard. Thus depending on the received data, a corresponding demodulator is activated to demodulate the received data and subsequently produces audio and video data.

Abstract: A method for de-interlacing is disclosed. The method generally includes the steps of (A) determining a plurality of target mode values for a target pixel being synthesized to convert a current field into a current frame, wherein at least two of the target mode values are based on both (i) a plurality of original pixels and (ii) a plurality of synthesized pixels in a plurality of synthesized frames, (B) generating a plurality of candidate values for the target pixel using a plurality of interpolation techniques that includes a motion estimation interpolation utilizing a particular one of the synthesized frames and (C) selecting a particular one of the candidate values for the target pixel in response to the target mode values.

Abstract: A method for de-interlacing is disclosed. The method generally includes the steps of (A) determining a plurality of target mode values for a target pixel being synthesized to convert a current field into a current frame, wherein at least two of the target mode values are based on both (i) a plurality of original pixels and (ii) a plurality of synthesized pixels in a plurality of synthesized frames, (B) generating a plurality of candidate values for the target pixel using a plurality of interpolation techniques that includes a motion estimation interpolation utilizing a particular one of the synthesized frames and (C) selecting a particular one of the candidate values for the target pixel in response to the target mode values.

Abstract: A system and method are provided for encoding and compressing video data. A memory device is configured to store video data, and a corresponding memory controller controls the storage of video data in the memory device. A frame buffer compression module compresses frame data received from a video module to be stored in the memory device according to the memory controller and decompresses compressed frame data received from the memory device according to the memory controller for use by a video module. The frame buffer compression module includes a frame buffer compression encoder configured to encode and compress frame data received from a video module for storage in memory according to the memory controller. The frame buffer also includes a corresponding frame buffer compression decoder configured to decode and decompress frame data received from memory according to the memory controller for use by a video module.