Abstract: A semiconductor device includes a substrate and a semiconductor structure that is located on the substrate and that includes a device portion including a semiconductor element, and a seal ring portion. The semiconductor element includes a first electrode and a second electrode. The seal ring portion surrounds the device portion and includes a conducting element. The conducting element includes an enhanced-High-Electron-Mobility-Transistor (eHEMT) that includes a first gate electrode electrically connected to the first electrode, a first source electrode electrically connected to the second electrode, and a first drain electrode electrically connect to the first electrode. A method for making the semiconductor device and a seal ring structure are also provided.

Abstract: The present disclosure provided a lateral field-effect transistor and its preparing method, relating to semiconductor technological field. A gate pad and a source pad configured by the lateral field transistor in a passive region extend from a first surface of a device functional layer to a surface of substrate respectively. The gate pad is isolated from the device functional layer and the substrate respectively. The source pad is shorted to the substrate. Therefore, through a capacitance structure formed between the gate pad and the source pad shorted to the substrate, the capacitance of a device that formed between the gate pad and source pad may be increased, thereby effectively alleviating the generated oscillation, reducing the loss of a power device, and avoiding the false turn-on of the lateral field-effect transistor.

Abstract: A Group III-V compound semiconductor device includes a Group III-V compound substrate and a passivation structure. The passivation structure is disposed on a surface of the Group III-V compound substrate and includes a scandium-nitrogen-containing layer and a scandium-oxygen-containing layer sequentially stacked in that order in a direction away from the surface of the Group III-V compound substrate.

Abstract: An epitaxial structure for a high-electron-mobility transistor includes a substrate, a nucleation layer, a buffer layered unit, a channel layer, and a barrier layer sequentially stacked on one another in such order. The buffer layered unit includes at least one multiple quantum well structure containing a plurality of p-i-n heterojunction stacks. Each of the p-i-n heterojunction stacks includes p-type, i-type, and n-type layers which are alternately stacked along a direction away from the nucleation layer, and which are made of materials respectively represented by chemical formulas of AlxGa(1-x)N, AlyGa(1-y)N, and AlzGa(1-z)N. For each of the p-i-n heterojunction stacks, x gradually decreases and z gradually increases along the direction away from the nucleation layer, and y is consistent and ranges from 0 to 0.7.

Abstract: A microelectronic device includes a substrate, at least two doped well regions, an epitaxial structure, and at least two power elements. The doped well regions are disposed in the substrate, and are spaced apart from each other. Each of the doped well regions has a doping type opposite to that of the substrate. The epitaxial structure is disposed on the substrate, and is in contact with the doped well regions. The power elements are disposed on the epitaxial structure opposite to the substrate, and are cascade connected with each other. A low potential terminal of each of the power elements is electrically connected to a respective one of the doped well regions. A method for making the microelectronic device is also provided.

Abstract: A microwave transistor has a patterned region between a source and a drain on a barrier layer. Within the patterned region, the surface of the barrier layer partially recessed downwards in the thickness direction to form a plurality of grooves. A gate covers the patterned region. The length of the gate is greater than the lengths of the grooves in the length direction of the gate, so as to completely cover the grooves. In one aspect, by arranging the grooves, the gate control capability of a component is improved and the short-channel effect is suppressed; in another aspect, an original heterostructure below the gate is preserved; in this way, the reduction of the conductive capability due to the reduction of the two-dimensional electron gas density is avoided; and accordingly the current output capability of the component is ensured while the short-channel effect is suppressed.

Abstract: An epitaxial structure for a high-electron-mobility transistor includes a substrate, a nucleation layer, a buffer layered unit, a channel layer, and a barrier layer sequentially stacked on one another in such order. The buffer layered unit includes at least one multiple quantum well structure containing a plurality of p-i-n heterojunction stacks. Each of the p-i-n heterojunction stacks includes p-type, i-type, and n-type layers which are alternately stacked along a direction away from the nucleation layer, and which are made of materials respectively represented by chemical formulas of AlxGa(1-x)N, AlyGa(1-y)N, and AlzGa(1-z)N. For each of the p-i-n heterojunction stacks, x gradually decreases and z gradually increases along the direction away from the nucleation layer, and y is consistent and ranges from 0 to 0.7.

Abstract: A Silicon Carbide (SiC) power device employing a heterojunction terminal includes: a cathode electrode, a substrate layer, an N-type SiC extension layer, an anode electrode, and a plurality of P-type structures disposed at interval. The plurality of P-type structures grow and form, via a heterogeneous epitaxy, using a P-type semiconductor material having a growth temperature less than that of SiC, and on the N-type SiC extension layer, and are evenly or unevenly distributed at periphery of the anode electrode, so as to form a heterogeneous terminal. Therefore, the embodiment effectively prevents impact on a doping characteristic of the N-type SiC extension layer, and can obtain a SiC device having a high breakdown voltage and low device turn-on voltage. Also provided is a manufacturing method of the SiC power device. The embodiment reduces requirements for a high-temperature or complex technique, provides a simple process, and reduces manufacturing costs.

Abstract: A microwave transistor has a patterned region between a source and a drain on a barrier layer. Within the patterned region, the surface of the barrier layer partially recessed downwards in the thickness direction to form a plurality of grooves. A gate covers the patterned region. The length of the gate is greater than the lengths of the grooves in the length direction of the gate, so as to completely cover the grooves. In one aspect, by arranging the grooves, the gate control capability of a component is improved and the short-channel effect is suppressed; in another aspect, an original heterostructure below the gate is preserved; in this way, the reduction of the conductive capability due to the reduction of the two-dimensional electron gas density is avoided; and accordingly the current output capability of the component is ensured while the short-channel effect is suppressed.

Abstract: The present application describes a vertical light-emitting diode (VLED) and its manufacture method that use the combination of a reflective layer, a transparent conducting layer and transparent dielectric layer as structural layers for promoting uniform current distribution and increasing light extraction. In the VLED, a transparent conducting layer is formed on a first outer surface of a stack of multiple group III nitride semiconductor layers. A transparent dielectric layer is then formed on a side of the transparent conducting layer opposite the side of the multi-layer structure. A first electrode structure is then formed on the transparent dielectric layer in electrical contact with the transparent conducting layer via a plurality of contact windows patterned through the transparent dielectric layer. The transparent conducting layer and the transparent dielectric layer are used as structural layers for improving light extraction.

Abstract: A method for fabricating a vertical light-emitting diode comprises forming a stack including a plurality of epitaxial layers on a patterned first substrate, placing a second substrate on the stack, removing the first substrate to expose the first surface, planarizing a first surface of the stack that was in contact with the patterned first substrate and has a pattern corresponding to a pattern provided on the first substrate to form a planarized second surface, and forming a first electrode in contact with a side of the second substrate that is opposite to the stack, and a second electrode in contact with the second surface of the stack. A roughening step can be performed to form uneven surface portions on a region of the second surface for improving light emission through the second surface of the stack.

Abstract: In a method of manufacturing a vertical type light-emitting diode, a multilayered structure of group III nitride semiconductor compounds is epitaxy deposited on an irregular surface of a substrate. The substrate is then removed to expose an irregular surface of the multilayered structure corresponding to the irregular surface of the substrate. A portion of the exposed irregular surface of the multilayered structure is then etched for forming an electrode contact surface on which an electrode layer is subsequently formed. With this method, no specific planarized region is required on the irregular surface of the substrate. As a result, planarization treatment of the substrate is not necessary. The same substrate with the irregular surface can be reused for fabricating vertical and horizontal light-emitting diodes.

Abstract: The present application describes a vertical light-emitting diode (VLED) and its manufacture method that use the combination of a reflective layer, a transparent conducting layer and transparent dielectric layer as structural layers for promoting uniform current distribution and increasing light extraction. In the VLED, a transparent conducting layer is formed on a first outer surface of a stack of multiple group III nitride semiconductor layers. A transparent dielectric layer is then formed on a side of the transparent conducting layer opposite the side of the multi-layer structure. A first electrode structure is then formed on the transparent dielectric layer in electrical contact with the transparent conducting layer via a plurality of contact windows patterned through the transparent dielectric layer. The transparent conducting layer and the transparent dielectric layer are used as structural layers for improving light extraction.

Abstract: In a method of manufacturing a vertical type light-emitting diode, a multilayered structure of group III nitride semiconductor compounds is epitaxy deposited on an irregular surface of a substrate. The substrate is then removed to expose an irregular surface of the multilayered structure corresponding to the irregular surface of the substrate. A portion of the exposed irregular surface of the multilayered structure is then etched for forming an electrode contact surface on which an electrode layer is subsequently formed. With this method, no specific planarized region is required on the irregular surface of the substrate. As a result, planarization treatment of the substrate is not necessary. The same substrate with the irregular surface can be reused for fabricating vertical and horizontal light-emitting diodes.

Abstract: The present invention discloses a surface roughening method for an LED substrate, which uses a grinding technology and an abrasive paper of from No. 300 to No. 6000 to grind the surface of a substrate to form a plurality of irregular concave zones and convex zones on the surface of the substrate. Next, a semiconductor light emitting structure is formed on the surface of the substrate. The concave zones and convex zones can scatter and diffract the light inside LED, reduce the horizontally-propagating light between the substrate and the semiconductor layer, decrease the probability of total reflection and promote LED light extraction efficiency.

Abstract: The present invention discloses a surface roughening method for an LED substrate, which uses a grinding technology and an abrasive paper of from No. 300 to No. 6000 to grind the surface of a substrate to form a plurality of irregular concave zones and convex zones on the surface of the substrate. Next, a semiconductor light emitting structure is formed on the surface of the substrate. The concave zones and convex zones can scatter and diffract the light inside LED, reduce the horizontally-propagating light between the substrate and the semiconductor layer, decrease the probability of total reflection and promote LED light extraction efficiency.