Abstract: An integrated circuit may include a reconfigurable functional circuit block coupled to a microcontroller. The microcontroller may monitor a trigger register that receives trigger signals at a reconfiguration portion. The trigger signals may initiate corresponding reconfiguration operations by triggering the execution of instructions in a reconfiguration sequence program to load appropriate configuration data to configuration registers. The configuration registers may determine the operating mode of the functional circuit block by activating a subcomponent module in the functional circuit block. By providing a reconfiguration port that has full control of the reconfiguration of the functional circuit block, sensitive information regarding the implementation of the functional circuit block, the microcontroller, and connections therebetween may be protected while simplifying the design process for a custom logic circuit generated based on the reconfigurable functional circuit block.

Abstract: An integrated circuit may include a reconfigurable functional circuit block coupled to a microcontroller. The microcontroller may monitor a trigger register that receives trigger signals at a reconfiguration portion. The trigger signals may initiate corresponding reconfiguration operations by triggering the execution of instructions in a reconfiguration sequence program to load appropriate configuration data to configuration registers. The configuration registers may determine the operating mode of the functional circuit block by activating a subcomponent module in the functional circuit block. By providing a reconfiguration port that has full control of the reconfiguration of the functional circuit block, sensitive information regarding the implementation of the functional circuit block, the microcontroller, and connections therebetween may be protected while simplifying the design process for a custom logic circuit generated based on the reconfigurable functional circuit block.

Abstract: The presently-disclosed solution enables continuous time linear equalizer (CTLE) tuning without needing to perform bit error rate (BER) measurements. Because time consuming BER measurements are avoided, the CTLE tuning may be performed more rapidly as to reduce substantially the time required for link training. Furthermore, this solution re-uses decision feedback equalizer (DFE) adaptation circuitry so as to be highly efficient in its implementation. One embodiment relates to a method that tunes the CTLE based on results from the adaptation of the tap values of the DFE. Another embodiment relates to an apparatus that includes an interface for a control module to control a setting of a CTLE and an adaptation engine for a DFE. The value for the setting of the CTLE is selected using the adapted tap 1 value of the DFE as a figure of merit. Other embodiments and features are also disclosed.

Abstract: A serializer is provided to serialize combined synchronization information and data blocks for transmission over the high-speed channel. A gearbox combines synchronization information with data blocks to present to the serializer. A scrambler scrambles data blocks to present to the gearbox. An encoding device stores a program that contains instructions to format the data blocks for sending over the high-speed channel. The formatting reduces a number of operations used to receive the data blocks by a receiver.

Abstract: A communication circuit comprises a plurality of receivers to receive the serial data from multiple lanes of a communication channel. The receivers may convert data received from the lanes from a serial to parallel format. Decoders may identify characters recovered from the different lanes, which collectively may define a word of width (i.e., character width) related to the number of lanes. Logic may determine when at least one of a start-of-frame and an end-of-frame character has been received. Parsing circuitry may then determine valid characters of a received word based on their placement relative to a start-of-frame character and/or an end-of-frame character. A controller may control when to present recovered data to at least one of storage registers or an output port, based on the character type identified by the decoder, its placement, an amount of characters parsed, and the number of characters already stored.