Abstract: Briefly, in accordance with one embodiment of the invention, a portable computing device that has a processor, a direct memory access (DMA) engine, and a display controller may transfer data with the DMA engine to the display. The DMA engine may transfer the data while the processor is in a standby mode and transfer data to the processor while the processor is executing instructions.

Abstract: A method and apparatus for calculation and storage of Single-Instruction-Multiple-Data (SIMD) saturation history information pursuant to instruction execution. A coprocessor instruction has a format identifying a saturating operation, a first source having packed data elements and a second source having packed data elements. The saturating operation is executed on the packed data elements of the first and second sources. Saturation flags are stored in bits zero through seven of the Wireless Coprocessor Saturation Status Flag (wCSSF) register to indicate if a result of the saturating operation saturated.

Abstract: A tightly coupled dual 16-bit multiply-accumulate (MAC) unit for performing single-instruction/multiple-data (SIMD) operations may forward an intermediate result to another operation in a pipeline to resolve an accumulating dependency penalty. The MAC unit may also be used to perform 32-bit×32-bit operations.

Abstract: A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes including a byte (8 bits), a half word (16 bits), a word (32 bits), and a double word (64 bits). Two other bits indicate a saturation type. A source register in the main processor and a destination register is in the coprocessor, those registers including data elements. The coprocessor instruction includes an opcode specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for the coprocessor instruction, the instruction to broadcast a data element from said source register to said destination register.

Abstract: In an embodiment, a functional unit including a compressor section and a 36-bit SIMD adder is used to perform a STMD four-pixel averaging instruction. The functional unit generates four four-pixel averages. Four pixel values and a rounding value are compressed into a sum and a carry vector. The two least significant bits of the sum vector and the LSB of the carry vector are dropped before being input to the 36-bit SIMD adder. The two resultant 8-bit vectors are added by the 36-bit adder to directly generate the average pixel value result.

Abstract: A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes including a byte (8 bits), a half word (16 bits), a word (32 bits), and a double word (64 bits). Two other bits indicate a saturation type.

Abstract: Briefly, in accordance with one embodiment of the invention, a portable computing device that has a processor, a direct memory access (DMA) engine, and a display controller may transfer data with the DMA engine to the display. The DMA engine may transfer the data while the processor is in a standby mode and transfer data to the processor while the processor is executing instructions.

Abstract: A method and apparatus for calculation and storage of Single-Instruction-Multiple-Data (SIMD) saturation history information pursuant to instruction execution. A coprocessor instruction has a format identifying a saturating operation, a first source having packed data elements and a second source having packed data elements. The saturating operation is executed on the packed data elements of the first and second sources. Saturation flags are stored in bits zero through seven of the Wireless Coprocessor Saturation Status Flag (wCSSF) register to indicate if a result of the saturating operation saturated.

Abstract: A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes including a byte (8 bits), a half word (16 bits), a word (32 bits), and a double word (64 bits). Two other bits indicate a saturation type.

Abstract: A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes including a byte (8 bits), a half word (16 bits), a word (32 bits), and a double word (64 bits). Two other bits indicate a saturation type.

Abstract: An adaptive color depth control may receive input signals from a power mode block, an ambient light sensor and/or a resource usage monitor to adjust the performance of a system through adaptation of the number of bits-per-pixel for each of the three primary colors supplied to a display. The spatial resolution may be adapted in a similar manner with inputs from the power mode block, ambient light sensor, and/or resource usage monitor.

Abstract: In an embodiment, a functional unit including a compressor section and a 36-bit SIMD adder is used to perform a SIMD four-pixel averaging instruction. The functional unit generates four four-pixel averages. Four pixel values and a rounding value are compressed into a sum and a carry vector. The tow least significant bits of the sum vector and the LSB of the carry vector are dropped before being input to the 36-bit SIMD adder. The two resultant 8-bit vectors are added by the 36-bit adder to directly generate the average pixel value result.

Abstract: A bit may be associated with the register to indicate whether or not the register has been updated. If the register has been updated, on the next context change, the contents of the register may be stored back to a memory. If no update has occurred, as determined by the update bit, then the unnecessary operation of saving the same file back to memory may be avoided, improving performance and saving power in some embodiments.

Abstract: A tightly coupled dual 16-bit multiply-accumulate (MAC) unit for performing single-instruction/multiple-data (SIMD) operations may forward an intermediate result to another operation in a pipeline to resolve an accumulating dependency penalty. The MAC unit may also be used to perform 32-bit×32-bit operations.

Abstract: A method and computer program for extracting and combining arithmetic flags utilized in the processing multiple data items in a single instruction multiple data (SIMD) capable processor. In a SIMD processor several pieces of data may be manipulated by the same instruction at any given moment. However, the results for the execution of this instruction vary according to the data being manipulated. The method and computer program allows a simple mechanism in which these arithmetic flags maybe extracted and combined so as to maximize processor efficiency while saving space, reducing power requirements and heat generated by the processor.

Abstract: A control apparatus and method is provided for controlling operations of functional units in systems. The control apparatus and method implement a set of operations that can include dependencies between the functional units of a system to complete each operation. For example, in an asynchronous digital processor, self-timing and inter-block communication are used to implement a self-timed scheduler. The self-timed scheduler and method implement an instruction set using a plurality of functional units of the asynchronous digital processor. A scheduler can include a scheduler decoder that decodes each instruction to generate functional unit schedule and control information, a communication device and a plurality of scheduler functional unit controllers, wherein each of the scheduler functional unit controllers corresponds to one of the plurality of functional units of a system.

Abstract: A power consumption control apparatus and method for an asynchronous system is provided that reduces power consumption by selecting one of a plurality of power consumption levels for the system. The power consumption levels can be determined based on work load requirements of the system and can be implemented for the system or portions thereof using a single block of the system. The asynchronous system includes a plurality of intercoupled functional units and a power control circuit coupled to a selected one of the plurality of functional units to determine at least one of a first and a second operating speed of a selected functional unit.

Abstract: A programmable circuit and method for a data processing apparatus is provided that allows an entire instruction or instruction set to be modified. According to the present invention, the instruction can be modified, for example, during initialization or execution. The programmable circuit for a data processing apparatus can include a plurality of functional units, each functional unit performing a set of prescribed operations. A programmable circuit that is capable of modifying an entire instruction. A controller that decodes a current instruction to perform a corresponding instruction task using the plurality of functional units and a communications device coupling the functional units, the programmable circuit and the controller.

Abstract: A condition detector for an asynchronous pipeline. Each stage in the pipeline includes a storage element for storing a single bit of data indicating whether or not the condition to be detected is set in that stage. The single bit in the storage element of one stage is transferred to the storage element of a succeeding stage in the pipeline when data is transferred between those stages. A detector detects whether or not any one of the storage elements of the pipeline stages indicates that the condition is set, and a condition set output is generated if any one of the storage elements of the pipeline stages indicates that the condition is set.