Abstract: A data processing apparatus comprising: a data processor for processing data in a secure and a non-secure mode, said data processor processing data in said secure mode having access to secure data that is not accessible to said data processor in said non-secure mode, and processing data in said secure mode being performed under control of a secure operating system and processing data in said non-secure mode being performed under control of a non-secure operating system; and a further processing device for performing a task in response to a request from said data processor, said task comprising processing data at least some of which is secure data; wherein said further processing device is responsive to receipt of a signal to suspend said task to initiate: processing of said secure data using a secure key; and storage of said processed secure data to a non-secure data store; and is responsive to receipt of a signal to resume said task to initiate: retrieval of said processed secure data from said non-secure da

Abstract: A data processing apparatus is provided comprising a processing device, and an N-way set associative cache for access by the processing device, each way comprising a plurality of cache lines for temporarily storing data for a subset of memory addresses of a memory device, and a plurality of dirty fields, each dirty field being associated with a way portion and being set when the data stored in that way portion is dirty data. Dirty way indication circuitry is configured to generate an indication of the degree of dirty data stored in each way. Further, staged way power down circuitry is responsive to at least one predetermined condition, to power down at least a subset of the ways of the N-way set associative cache in a plurality of stages, the staged way power down circuitry being configured to reference the dirty way indication circuitry in order to seek to power down ways with less dirty data before ways with more dirty data.

Abstract: A data processor for processing data in a secure mode having access to secure data that is not accessible to the data processor when processing data in the non-secure mode. A further processing device for performing a task in response to a request from the data processor issued from the non-secure mode. The further processing device including a secure data store not accessible to processes running on the data processor when in the non-secure mode. Prior to issuing requests, the data processor in the secure mode performs a set up operation on the further data processing device storing secure data in the secure data store. In response to receipt of the request from the data processor operating in the non-secure mode, the further data processing device performs the task using data stored in the secure data store to access any secure data required.

Abstract: A cache device is provided for use in a data processing apparatus to store data values for access by an associated master device. Each data value has an associated memory location in a memory device, and the memory device is arranged as a plurality of blocks of memory locations, with each block having to be activated before any data value stored in that block can be accessed. The cache device comprises regular access detection circuitry for detecting occurrence of a sequence of accesses to data values whose associated memory locations follow a regular pattern.

Abstract: A cache device is provided for use in a data processing apparatus to store data values for access by an associated master device. Each data value has an associated memory location in a memory device, and the memory device is arranged as a plurality of blocks of memory locations, with each block having to be activated before any data value stored in that block can be accessed. The cache device comprises regular access detection circuitry for detecting occurrence of a sequence of accesses to data values whose associated memory locations follow a regular pattern.

Abstract: A data processing system in the form of an integrated circuit includes a general purpose programmable processor and a hardware accelerator. A shared memory management unit provides memory management operations on behalf of both of the processor core and the hardware accelerator. The processor and the hardware accelerator share a memory system. A first communication channel between the processor and the hardware accelerator communicates at least control signals therebetween. A second communication channel coupling the hardware accelerator and the memory system allows the hardware accelerator to perform its own data access operations upon the memory system.

Abstract: A processing system 1 including a memory 10 and a cache memory 4 is provided with a page status unit 40 for providing a cache controller with a page open indication indicating one or more open pages of data values in memory. At least one of one or more cache management operations performed by the cache controller is responsive to the page open indication so that the efficiency and/or speed of the processing system can be improved.

Abstract: A data processing apparatus 2 includes a programmable general purpose processor 10 coupled to a hardware accelerator 12. A memory system 14, 6, 8 is shared by the processor 10 and the hardware accelerator 12. Memory system monitoring circuitry 16 is responsive to one or more predetermined operations performed by the processor 10 upon the memory system 14, 6, 8 to generate a trigger to the hardware accelerator 12 for it to halt its processing operations and clean any data values held as temporary variables within registers 20 of the hardware accelerator back to the memory system 14, 6, 8.

Abstract: A processing system 1 including a memory 10 and a cache memory 4 is provided with a page status unit 40 for providing a cache controller with a page open indication indicating one or more open pages of data values in memory. At least one of one or more cache management operations performed by the cache controller is responsive to the page open indication so that the efficiency and/or speed of the processing system can be improved.

Abstract: A data processing system in the form of an integrated circuit 2 includes a general purpose programmable processor 4 and a hardware accelerator 6. A shared memory management unit 10 provides memory management operations on behalf of both of the processor core 4 and the hardware accelerator 6. The processor 4 and the hardware accelerator 6 share a memory system 8. A first communication channel 12 between the processor 4 and the hardware accelerator 6 communicates at least control signals therebetween. A second communication channel 14 coupling the hardware accelerator 6 and the memory system 8 allows the hardware accelerator 6 to perform its own data access operations upon the memory system 8.

Abstract: A data processing apparatus comprising a data processor for processing data in a secure and a non-secure mode, said data processor processing data in said secure mode having access to secure data that is not accessible to said data processor processing data in said non-secure mode; and a further processing device for performing a task in response to a request from said data processor issued from said non-secure mode, said task comprising processing data at least some of which is secure data, said further processing device comprising a secure data store, said secure data store not being accessible to processes running on said data processor in non-secure mode; wherein prior to issuing any of said requests said data processor is adapted to perform a set up operation on said further data processing device, said set up operation being performed by said data processor operating in said secure mode and comprising storing secure data in said secure data store on said further processing device, said secure data being

Abstract: A data processing apparatus comprising: a data processor for processing data in a secure and a non-secure mode, said data processor processing data in said secure mode having access to secure data that is not accessible to said data processor in said non-secure mode, and processing data in said secure mode being performed under control of a secure operating system and processing data in said non-secure mode being performed under control of a non-secure operating system; and a further processing device for performing a task in response to a request from said data processor, said task comprising processing data at least some of which is secure data; wherein said further processing device is responsive to receipt of a signal to suspend said task to initiate: processing of said secure data using a secure key; and storage of said processed secure data to a non-secure data store; and is responsive to receipt of a signal to resume said task to initiate: retrieval of said processed secure data from said non-secure da

Abstract: A data processing apparatus 2 includes a programmable general purpose processor 10 coupled to a hardware accelerator 12. A memory system 14, 6, 8 is shared by the processor 10 and the hardware accelerator 12. Memory system monitoring circuitry 16 is responsive to one or more predetermined operations performed by the processor 10 upon the memory system 14, 6, 8 to generate a trigger to the hardware accelerator 12 for it to halt its processing operations and clean any data values held as temporary variables within registers 20 of the hardware accelerator back to the memory system 14, 6, 8.

Abstract: The present invention provides an apparatus and method for processing data, the apparatus comprising a plurality of asynchronous control circuits, each asynchronous control circuit employing a request-acknowledge control loop to control data flow within that asynchronous control circuit, and being arranged to exchange data signals with at least one other of said plurality of asynchronous control circuits. Further, a first of said asynchronous control circuits includes a halt circuit for blocking a control signal in the control loop of the first asynchronous control circuit, thereby preventing the exchange of data signals with said at least one other of said plurality of asynchronous control circuits so as to cause the control loops of said plurality of asynchronous control circuits to become blocked. The present invention is based on an asynchronous design, which only causes transitions in the circuit in response to a request to carry out useful work.