Abstract: Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting logic includes interconnecting tiles and may further include interfacing logic. The interconnecting tiles provide selective connectivity between inputs and/or outputs of the fixed logic circuit and interconnect of the programmable logic fabric. The interfacing logic, when included, provides logic circuitry that conditions data transfers between the fixed logic circuit and the programmable logic fabric. In one operation, the programmable logic fabric is configured prior to the startup/boot sequence of the fixed logic circuit. In another operation, the fixed logic circuit is started up and is employed to configure the programmable logic fabric.

Abstract: Method and apparatus for generating a test program for an integrated circuit having an embedded processor. One embodiment has a system which includes an embedded microprocessor; a plurality of assembly language instructions stored in a memory, where the assembly language instructions substantially exercise a critical path or a path closest to the critical path in the embedded microprocessor; and programmable test circuitry having a programmable clock circuit for providing a multiplied clock signal to the embedded microprocessor in order to execute the assembly language instructions.

Abstract: Automatic antenna diode insertion for integrated circuits is described. In an example, at least a portion of an integrated circuit is defined by a block of standard cells selected from a cell library. A diode circuit is associated with at least one input port of the block of standard cells to form an augmented block. The augmented block is then implemented on a chip to form the integrated circuit. In another example, an integrated circuit is formed by associating a diode circuit with each primary input port of an embedded logic circuit that defines a portion of the integrated circuit. A remaining portion of the integrated circuit is defined by existing logic circuitry. Components of the embedded logic circuit are placed on a chip and conductors are routed connecting the components. The embedded logic circuit is then integrated with the existing circuitry onto the chip.

Abstract: Method and apparatus for generating a test program for an integrated circuit having an embedded processor. One embodiment has a system which includes an embedded microprocessor; a plurality of assembly language instructions stored in a memory, where the assembly language instructions substantially exercise a critical path or a path closest to the critical path in the embedded microprocessor; and programmable test circuitry having a programmable clock circuit for providing a multiplied clock signal to the embedded microprocessor in order to execute the assembly language instructions.

Abstract: Method and apparatus for generating a test program for a programmable logic device having an embedded processor. Predetermined code is obtained to exercise at least one speed limiting path identified. To the predetermined code is added wrapper code to provide the test program, the wrapper code in part for loading the predetermined code into cache of the embedded processor for testing the at least one speed limiting path of the embedded processor identified.

Abstract: A circuit that includes a core device that is embedded within fixed interfacing logic circuitry that, in turn, is embedded in an FPGA fabric. The FPGA fabric may be configured into a test mode of operation to test either the embedded device or fixed logic devices formed within the fixed interfacing logic. While the FPGA is configured in a test mode, test circuitry and communication paths are made present within the fixed interfacing logic circuitry to facilitate the testing. Additionally, the test circuitry comprises isolation circuitry that is formed between various modules and circuits that are to be tested to isolate the device under test and to produce test signals thereto and there from during testing operations.

Abstract: A circuit that includes a core device that is embedded within fixed interfacing logic circuitry that, in turn, is embedded in an FPGA fabric. The FPGA fabric may be configured into a test mode of operation to test either the embedded device or fixed logic devices formed within the fixed interfacing logic. While the FPGA is configured in a test mode, test circuitry and communication paths are made present within the fixed interfacing logic circuitry to facilitate the testing. Additionally, the test circuitry comprises isolation circuitry that is formed between various modules and circuits that are to be tested to isolate the device under test and to produce test signals thereto and there from during testing operations.

Abstract: A circuit that includes a core device that is embedded within fixed interfacing logic circuitry that, in turn, is embedded in an FPGA fabric. The FPGA fabric may be configured into a test mode of operation to test either the embedded device or fixed logic devices formed within the fixed interfacing logic. While the FPGA is configured in a test mode, test circuitry and communication paths are made present within the fixed interfacing logic circuitry to facilitate the testing. Additionally, the test circuitry comprises isolation circuitry that is formed between various modules and circuits that are to be tested to isolate the device under test and to produce test signals thereto and therefrom during testing operations.

Abstract: Method and apparatus for placement of vias is described. More particularly, source power and ground vias are placed in partial response to locations where conductive lines cross over a reserved region. The reserved region is reserved for an embedded device, and is reserved in a layout database of a host device.

Abstract: Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting logic includes interconnecting tiles and may further include interfacing logic. The interconnecting tiles provide selective connectivity between inputs and/or outputs of the fixed logic circuit and the interconnects of the programmable logic fabric. The interfacing logic, when included, provides logic circuitry that conditions data transfers between the fixed logic circuit and the programmable logic fabric.

Abstract: Method and apparatus for an insertable block tile is described. More particularly, a reserved area in an integrated circuit layout is removed, and terminated conductive line information is extracted from a layout database affected by the removal. The terminated conductive line information is used to create extensions or pins of the conductive lines terminated, as well as to identify signals associated with those terminated conductive lines. These physical or layout names and coordinates are mapped and then translated to logic names and coordinates for placement and routing to create the insertable block tile.