Abstract: A vector data transfer instruction is provided for triggering a data transfer between storage locations corresponding to a contiguous block of addresses and multiple data elements of at least one vector register. The instruction specifies a start address of the contiguous block using a base register and an immediate offset value specifies as a multiple of the size of the contiguous block of addresses. This is useful for loop unrolling which can help to improve performance of vectorised code by combining multiple iterations of a loop into a single iteration of an unrolled loop, to reduce the loop control overhead.

Abstract: First and second types of vector load instruction are provided. For the first type, a response action is performed when an exceptional condition is detected for a load operation performed for a first active data element of at least one vector register, but when the exceptional condition is detected for an active data element other than the first active data element, the response action is suppressed and element identifying information is stored identifying the element which caused the exceptional condition. For the second type, the response action is suppressed and the element identifying information is stored when the exceptional condition arises for any active data element. This approach is useful for allowing loop speculation and loop unrolling to be used together to improve performance of vectorised code.

Abstract: Data processing apparatus comprises processing circuitry to selectively apply a vector processing operation to data items at positions within data vectors according to the states of a set of respective predicate flags associated with the positions, the data vectors having a data vector processing order, each data vector comprising a plurality of data items having a data item order, the processing circuitry comprising: instruction decoder circuitry to decode program instructions; and instruction processing circuitry to execute instructions decoded by the instruction decoder circuitry; wherein the instruction decoder circuitry is responsive to a propagation instruction to control the instruction processing circuitry to derive a set of predicate flags applicable to a current data vector in dependence upon a set of predicate flags applicable to a preceding data vector in the data vector processing order, wherein when one or more last-most predicate flags of the set applicable to the preceding data vector are inac

Abstract: An apparatus and a method are provided for performing a splice operation, the apparatus having a set of vector registers and one or more control registers. Processing circuitry is arranged to execute a sequence of instructions including a splice instruction that identifies at least a first vector register and at least one control register. The first vector register stores a first vector of data elements having a vector length, and the at least one control register stores control data identifying one or more data elements occupying sequential data element positions within the first vector of data elements.

Abstract: A data processing system (2) supports vector processing operations performed upon vector operands comprising a plurality of vector operand elements. The data processing system includes a processor (4) having an instruction decoder (14) which decodes mixed-element-sized vector arithmetic instructions to generate control signals (16) which control processing circuitry (18) to perform arithmetic operations upon a first vector of first source operand elements ai of a first bit size A, and a second vector of second source operand elements bj of a second bit size B. The second bit size B is greater than the first bit size A.

Abstract: A data processing system (2) includes processing circuitry (18) and decoder circuitry (14) for decoding program instructions and controlling the processor circuitry. The decoder circuitry is responsive to a vector operand bit size dependant instruction executed within a selected exception level state of a hierarchy of exception level states to control the processing circuitry to perform processing with a vector operand bit size governed by a limiting value of the vector operand bit size associated with the currently selected exception level state, any programmable limit value set for an exception level state closer to a top exception level state within the hierarchy and the implemented limit.

Abstract: A data processing system (2) supports non-speculative execution of vector load instructions that perform at least one contingent load of a data value. Fault detection circuitry (26) serves to detect whether a contingent load is fault-generating contingent load or a fault-free contingent load. Contingent load suppression circuitry (28) detects and suppresses a fault-free contingent load that matches a predetermined criteria that may result in an undesired change of architectural state (undesired side-effect). Examples of such predetermined criteria are that the contingent load is to a non-memory device or that the contingent load will trigger a diagnostic response such as entry of a halting debug halting mode or triggering of a debug exception.

Abstract: A data processing system 2 supporting vector processing operations uses scaling vector length querying instructions. The scaling vector length querying instructions return a result which is dependent upon a number of elements in a vector for a variable vector element size specified by the instruction and multiplied by a scaling value specified by the instruction. The scaling vector length querying instructions may be in the form of count instructions, increment instructions or decrement instructions. The instructions may include a pattern constraint applying a constraint, such as modulo(M) or power of 2 to the partial result value representing the number of vector elements provided for the register element size specified for the instruction.

Abstract: An apparatus performs an operation on a register, and then conditionally selects either that register or a further register on which no operation has been performed. The apparatus includes a decoder that decodes a conditional select instruction that specifies a primary source register, a secondary source register, a destination register, a condition, and an operation to be performed on a data element from the secondary source register. A data processor is responsive to the decoded conditional select instruction and the condition (i) having a predetermined outcome to perform the operation on the data element from the secondary source register to form a resultant data element and to store the resultant data element in the destination register, and (ii) not having the predetermined outcome to form the resultant data element from the data element from the primary register and to store the resultant data element in the destination register.

Abstract: An apparatus and method are provided for transferring a plurality of data structures between memory and a plurality of vector registers, each vector register being arranged to store a vector operand comprising a plurality of data elements. Access circuitry is used to perform access operations to move data elements of vector operands between the data structures in memory and specified vector registers, each data structure comprising multiple data elements stored at contiguous addresses in the memory.

Abstract: An apparatus performs an operation on a register, and then conditionally selects either that register or a further register on which no operation has been performed. The apparatus includes a decoder that decodes a conditional select instruction that specifies a primary source register, a secondary source register, a destination register, a condition, and an operation to be performed on a data element from the secondary source register. A data processor is responsive to the decoded conditional select instruction and the condition (i) having a predetermined outcome to perform the operation on the data element from the secondary source register to form a resultant data element and to store the resultant data element in the destination register, and (ii) not having the predetermined outcome to form the resultant data element from the data element from the primary register and to store the resultant data element in the destination register.

Abstract: A data processing apparatus, method and computer program that perform an operation on one data element such as a register and conditionally select either that register or a further register on which no operation has been performed. The apparatus includes an instruction decoder configured to decode at least one conditional select instruction specifying a primary source register, a secondary source register, a destination register, a condition, and an operation to be performed on a data element from the secondary source register. Data processing operations are controlled by the instruction decoder and the data processor is responsive to the decoded at least one conditional select instruction where the condition does not have the predetermined outcome to form the resultant data element from the data element from the primary register and to store the resultant data element in the destination register.

Abstract: A data processing apparatus comprises a processing circuit and instruction decoder. A bitfield manipulation instruction controls the processing apparatus to generate at least one result data element from corresponding first and second source data elements. Each result data element includes a portion corresponding to a bitfield of the corresponding first source data element. Bits of the result data element that are more significant than the inserted bitfield have a prefix value that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element, and a third prefix value corresponding to a sign extension of the bitfield of the first source data element.

Abstract: A data processing apparatus comprises a processing circuit and instruction decoder. A bitfield manipulation instruction controls the processing apparatus to generate at least one result data element from corresponding first and second source data elements. Each result data element includes a portion corresponding to a bitfield of the corresponding first source data element. Bits of the result data element that are more significant than the inserted bitfield have a prefix value that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element, and a third prefix value corresponding to a sign extension of the bitfield of the first source data element. Bitwise logical instructions are also described.

Abstract: An apparatus and method are provided for transferring a plurality of data structures between memory and a plurality of vector registers, each vector register being arranged to store a vector operand comprising a plurality of data elements. Access circuitry is used to perform access operations to move data elements of vector operands between the data structures in memory and specified vector registers, each data structure comprising multiple data elements stored at contiguous addresses in the memory.

Abstract: A data processing apparatus is provided comprising processing circuitry and an instruction decoder responsive to program instructions to control processing circuitry to perform the data processing. The instruction decoder is responsive to an address calculating instruction to perform an address calculating operation for calculating a partial address result from a non-fixed reference address and a partial offset value such that a full address specifying a memory location of an information entity is calculable from said partial address result using at least one supplementary program instruction. The partial offset value has a bit-width greater than or equal to said instruction size and is encoded within at least one partial offset field of said address calculating instruction. A corresponding data processing method, virtual machine and computer program product are also provided.

Abstract: A data processing apparatus comprises a processing circuit and instruction decoder. A bitfield manipulation instruction controls the processing apparatus to generate at least one result data element from corresponding first and second source data elements. Each result data element includes a portion corresponding to a bitfield of the corresponding first source data element. Bits of the result data element that are more significant than the inserted bitfield have a prefix value that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element, and a third prefix value corresponding to a sign extension of the bitfield of the first source data element.

Abstract: A data processing apparatus comprises a processing circuit and instruction decoder. A bitfield manipulation instruction controls the processing apparatus to generate at least one result data element from corresponding first and second source data elements. Each result data element includes a portion corresponding to a bitfield bf of the corresponding first source data element. Bits of the result data element that are more significant than the inserted bitfield have a prefix value that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element, and a third prefix value corresponding to a sign extension of the bitfield of the first source data element.

Abstract: A data processing system includes a processor core and a memory. The processor core includes processing circuitry controlled by control signals generated by decoder circuitry which decodes program instructions. The program instructions include mixed operand size instructions (either load/store instructions or arithmetic instructions) which have a first input operand of a first operand size and a second input operand of a second input operand size where the second operand size is smaller than the first operand size. The processing performed first converts the second operand so as to have the first operand size. The processing then generates a third operand using as inputs the first operand of the first operand size and the second operand now converted to have the first operand size.

Abstract: A data processing apparatus is provided comprising processing circuitry and an instruction decoder responsive to program instructions to control processing circuitry to perform the data processing. The instruction decoder is responsive to an address calculating instruction to perform an address calculating operation for calculating a partial address result from a non-fixed reference address and a partial offset value such that a full address specifying a memory location of an information entity is calculable from said partial address result using at least one supplementary program instruction. The partial offset value has a bit-width greater than or equal to said instruction size and is encoded within at least one partial offset field of said address calculating instruction. A corresponding data processing method, virtual machine and computer program product are also provided.