Abstract: A data processing system includes a microcomputer (1) provided with an address latch (5). The microcomputer is provided with a watch-dog arrangement which comprises the usual clocked counter (17) an output (Qn) of which is coupled to a reset input (RST) of the microcomputer. In order to increase the number of malfunctions to which the watch-dog responds the microcomputer is arranged to repeatedly generate reset signals each in the form of a complete byte X or Y which alternate. These are applied to an input (30) of a comparator (10) which compares them with identical bytes fed to a further input 31 via a switched multiplexer (13), the comparator output (37) being connected to a reset input (RS) of the counter. Each time this occurs the microcomputer strobes the watch-dog by applying its address to a further input (46, 22).

Abstract: A data processing system includes a microcomputer (1) and a watchdog circuit arrangement which includes a clocked counter (17) having an output Q.sub.n which is coupled to a reset input (RST) of the microcomputer. In order to increase the kinds of microcomputer malfunctions to which the watchdog circuit responds, the microcomputer is programmed to repeatedly generate predetermined reset signal bytes within respective time windows, such time windows corresponding to periods during which a further output Q.sub.n-1 of the counter is logic "1". The reset signal byte supplied by the microcomputer is compared by a comparator (10) with the predetermined reset signal byte, which is supplied thereto by a switched multiplexor (13), and if they match the output signal from the comparator resets the counter. Each time this occurs the microcomputer strobes the watchdog circuit by applying its address to a further input (22, 46) thereof.