Abstract: Techniques are disclosed for handling control transfer instructions in pipelined processors. Such instructions may cause the sequence of subsequent instructions to change, and thus may require subsequent instructions to be deleted from the processor's pipeline. Pre-decode means (110) are provided for at least partially decoding control transfer instructions early in the pipeline. Subsequent instructions can then be prevented from progressing through the pipeline. The mechanism required to delete unwanted instructions is thereby simplified.

Abstract: Mapping circuitry (40) comprises a first candidate output value producing unit (42) which produces a first candidate output value (Cl) that differs by a first offset value (x) from a received input value (r). During operation of the first candidate output value producing unit (42) a second candidate output value producing unit (44) produces a second candidate output value (C2) that differs by a second offset value (y) from the received input value (r). One of the first and second candidate output values is within a preselected range of allowable output values and the other is outside that range. An in-range value determining unit (46) determines which one of the first and second candidate output values is within the range, and an output value selection unit (48) selects this value as the output value (p) corresponding to the received input value (r).

Abstract: A processor has respective first and second external instruction formats (F1, F2) in which instructions (add, load) are received by the processor. Each instruction has an opcode (e.g. 1011) which specifies an operation to be executed. Each external format has one or more preselected opcode bits (F1:i+1˜i+4; F2:i+1˜i+3) in which the opcode appears. The processor also has an internal instruction format (G1) into which instructions in the external formats are translated prior to execution of the operation. A first operation (add) is specifiable in both the first and second external formats (F1, F2), and a second operation (load) is specifiable in the second external format (F2). The first and second operations have distinct opcodes (101, 011) in the second external format. In each of the preselected opcode bits which the first and second external formats have in common (i+1˜i+3), the opcodes of the first operation (101) in the two external formats are identical.

Abstract: Instructions of a program are stored in compressed form in a program memory (12). In a processor which executes the instructions, a program counter (50) identifies a position in the program memory. An instruction cache (40) has cache blocks, each for storing one or more instructions of the program in decompressed form. A cache loading unit (42) includes a decompression section (44) and performs a cache loading operation in which one or more compressed-form instructions are read from the position in the program memory identified by the program counter and are decompressed and stored in one of the said cache blocks of the instruction cache. A cache pointer (52) identifies a position in the instruction cache of an instruction to be fetched for execution. An instruction fetching unit (46) fetches an instruction to be executed from the position identified by the cache pointer.

Abstract: A processor has respective first and second external instruction formats (F1, F2) in which instructions (add, load) are received by the processor. Each instruction has an opcode (e.g. 1011) which specifies an operation to be executed. Each external format has one or more preselected opcode bits (F1: i+1˜i+4; F2: i+1˜i+3) in which the opcode appears. The processor also has an internal instruction format (G1) into which instructions in the external formats are translated prior to execution of the operation. A first operation (add) is specifiable in both the first and second external formats F1, F2), and a second operation (load) is specifiable in the second external format (F2). The first and second operations have distinct opcodes (101, 011) in the second external format. In each of the preselected opcode bits which the first and second external formats have in common (i+1˜i+3), the opcodes of the first operation (101) in the two external formats are identical.

Abstract: Instructions of a program are stored in compressed form in a program memory. A cache loading unit includes a decompression section and performs a cache loading operation in which one or more compressed-form instructions are read from the position in the program memory identified by the program counter and are decompressed and stored in one of the said cache blocks of the instruction cache. When a cache miss occurs because the instruction to be fetched is not present in the instruction cache, a cache loading unit performs such a cache loading operation. An updating unit updates the program counter and cache pointer in response to the fetching of instructions so as to ensure that the position identified by the said program counter is maintained consistently at the position in the program memory at which the instruction to be fetched from the instruction cache is stored in compressed form.

Abstract: Processors comprising a plurality of pipelines are disclosed, each pipeline having a plurality of pipeline stages (142, 146) for executing an instruction on successive clock cycles. The processors include distributed stall control circuitry (148, 150, 152, 154) which allow an instruction in one pipeline to become temporarily out of step with an instruction in another pipeline. This may allow time for a global signal, such as a global stall signal, to be distributed.

Abstract: A processor includes a series of predicate registers 135. Each predicate register is switchable between at least respective first and second states and each is assignable to one or more predicated-execution instructions. A control information holding unit 131 holds items of control information which correspond respectively to the predicate registers. An operating unit 133 is provided for each one of the predicate registers and receives items of control information Li and Li+1 and items of state information Pi, Pi?1. Each operating unit is operable to perform a selected state determining operation in which the state of its own predicate register is determined in dependence upon the received items. The operating units operate in parallel with one another to perform respective such state determining operations. The state determining operations can be used to bring about state changes required in prologue, kernel and epilogue stages of a software-pipelined loop.

Abstract: A processor, such as a VLIW processor capable of software-pipeline execution, includes an instruction issuing unit 10 for issuing, in a predetermined sequence, instructions to be executed. The sequence of instructions includes preselected value-producing instructions which, when executed, produce respective values. Instruction executing units 14, 16, 18 execute the issued instructions. A register file 20 has a set of registers, for storing values produced by the executed instructions. In operation the processor assigns the values produced by the value-producing instructions respective sequence numbers according to the order of issuance of their respective value-producing instructions. Each produced value is allocated one of the registers, for storing that produced value, in dependence upon the sequence number assigned to that value. The registers may be renamed each time a value-producing instruction is issued.

Abstract: Mapping circuitry (40) comprises a first candidate output value producing unit (42) which produces a first candidate output value (C1) that differs by a first offset value (x) from a received input value (r). A second candidate output value producing unit (44) operates, during operation of the first candidate output value producing unit (42) to produce the first candidate output value (C1), to produce a second candidate output value (C2) that differs by a second offset value (y) from the received input value (r). The first and second offset values (x, y) are such that a difference between them is equal to a difference between respective output-range limit values defining the limits of a preselected range of allowable values, and such that, for any input value (r) within a preselected range of allowable input values, one of the first and second candidate output values (C1, C2) is within the preselected output-value range and the other of those two values is outside that range.

Abstract: Mapping circuitry (40) comprises a first candidate output value producing unit (42) which produces a first candidate output value (C1) that differs by a first offset value (x) from a received input value (r). During operation of the first candidate output value producing unit (42) a second candidate output value producing unit (44) produces a second candidate output value (C2) that differs by a second offset value (y) from the received input value (r). One of the first and second candidate output values is within a preselected range of allowable output values and the other is outside that range. An in-range value determining unit (46) determines which one of the first and second candidate output values is within the range, and an output value selection unit (48) selects this value as the output value (p) corresponding to the received input value (r).

Abstract: A processor or processor core has register file circuitry having a plurality of physical registers and a plurality of tag storing portions corresponding respectively to the physical registers. Each tag storing portion stores a tag representing a logical register ID allocated to the corresponding physical register. A register selection unit receives a logical register ID and selects one of the logical registers whose tag matches the received logical register ID. A tag changing unit changes the stored tags so as to change a mapping between at least one logical register ID and one of the physical registers. Such register circuitry permits a mapping between logical register IDs and physical registers to be changed quickly efficiently and can permit a desired physical register to be selected quickly.

Abstract: A processor, and a method of accessing memory in a processor, are disclosed. The processor is arranged to generate virtual addresses for conversion into physical addresses for accessing physical memory, the physical memory comprising a first memory portion (101), and a second memory portion which is part of the same memory level as the first memory portion. When a virtual address is generated, part of that virtual address is converted into a partial physical address and a memory location in the first memory portion (101) is accessed using the partial physical address. In parallel with the memory access, a check may be carried out to determine whether the partial physical address is correct.

Abstract: A processor is capable of executing a software-pipelined loop. A plurality of registers (20) store values produced and consumed by executed instructions. A register renaming unit (32) renames the registers during execution of the loop. In the event that a software-pipelined loop requires zero iterations, the registers are renamed in a predetermined way to make the register allocation consistent with that which occurs in the normal case in which the loop has one or more iterations. This is achieved by carrying out an epilogue phase only of the loop with the instructions in the loop schedule turned off so that their results do not commit. The issuance of the instructions in the epilogue phase brings about the predetermined renaming automatically. The number of epilogue iterations may be specified in a loop instruction used to start up the loop.

Abstract: Processors comprising a plurality of pipelines are disclosed, each pipeline having a plurality of pipeline stages (142, 146) for executing an instruction on successive clock cycles. The processors include distributed stall control circuitry (148, 150, 152, 154) which allow an instruction in one pipeline to become temporarily out of step with an instruction in another pipeline. This may allow time for a global signal, such as a global stall signal, to be distributed.

Abstract: A processor, operable to execute instructions on a predicated basis, includes a series of predicate registers (135), a control information holding unit (131) and a plurality of operating units (133). Each predicate register of the series (135) is switchable between at least respective first and second states and each is assignable to one or more predicated-execution instructions. The control information holding unit (131) holds items of control information which correspond respectively to the predicate registers, and each operating unit also corresponds individually to one of the predicate registers. Each operating unit has a first control input connected to the control information holding unit (131) for receiving the control-information item corresponding to its unit's own corresponding predicate register and also has a second control input connected for receiving the control-information item corresponding to a further one of the predicate registers.

Abstract: Register file circuitry, for use in a processor or processor core, comprises a plurality of physical registers (320-32D-1) and a plurality of tag storing portions (340-34D-1) corresponding respectively to the physical registers. Each tag storing portion stores a tag representing a logical register ID allocated to the corresponding physical registers.

Abstract: A processor has respective first and second external instruction formats (F1, F2) in which instructions (add, load) are received by the processor. Each instruction has an opcode (e.g. 1011) which specifies an operation to be executed. Each external format has one or more preselected opcode bits (F1:i+1˜i+4; F2:i+1˜i+3) in which the opcode appears. The processor also has an internal instruction format (G1) into which instructions in the external formats are translated prior to execution of the operation.

Abstract: Instructions of a program are stored in compressed form in a program memory (12). In a processor which executes the instructions, a program counter (50) identifies a position in the program memory. An instruction cache (40) has cache blocks, each for storing one or more instructions of the program in decompressed form. A cache loading unit (42) includes a decompression section (44) and performs a cache loading operation in which one or more compressed-form instructions are read from the position in the program memory identified by the program counter and are decompressed and stored in one of the said cache blocks of the instruction cache. A cache pointer (52) identifies a position in the instruction cache of an instruction to be fetched for execution. An instruction fetching unit (46) fetches an instruction to be executed from the position identified by the cache pointer.

Abstract: Mapping circuitry (40) comprises a first candidate output value producing unit (42) which produces a first candidate output value (C1) that differs by a first offset value (x) from a received input value (r). A second candidate output value producing unit (44) operates, during operation of the first candidate output value producing unit (42) to produce the first candidate output value (C1), to produce a second candidate output value (C2) that differs by a second offset value (y) from the received input value (r). The first and second offset values (x, y) are such that a difference between them is equal to a difference between respective output-range limit values defining the limits of a preselected range of allowable values, and such that, for any input value (r) within a preselected range of allowable input values, one of the first and second candidate output values (C1, C2) is within the preselected output-value range and the other of those two values is outside that range.