Abstract: The disclosure is concerned with a receiver module (21) for wireless power transmission. The receiver module (21) comprises at least three transformer circuits (T) for transforming a received power transmission signal (Vin) into a supply signal (Vout) for a connectable energy storage device, such as a battery (23). The transformer circuits (T) are connected in series on a primary side (I). Due to a respective coupling capacitance (Cps1 to Cps4), each of the transformer circuits (T) may be unbalanced with respect to their output signals (V1, V2, V3, V4). To balance the output signals (V1, V2, V3, V4), which are used to provide the supply signal (Vout), at least two bypass devices (B) comprising at least one bypass capacitor (Cpp1, Cpp4) are connected in parallel to the first and last of the transformer circuits (T) in the serial connection.

Abstract: A method of operating an inverter circuit in a wireless power transmission device that may include at least one half-bridge with two switching units that each have a parasitic capacitance. In a respective half-bridge, the first switching unit links a plus potential (V+) of a DC source to a half-bridge node and the second switching unit links the half-bridge node to a minus potential (V?) of the DC source. A resonant circuit for the wireless power transmission is connected as a load to the respective half-bridge node, wherein the resonant circuit may include a transmission coil and at least one capacitive element.

Abstract: Efficient measures to improve electrical performance in a mobile side output circuitry of a wireless power transmission system are provided. The mobile side circuitry of the wireless power transmission system has a mobile side transformer stage comprising at least one primary side winding and a plurality of secondary side windings. To the plurality of secondary side windings there are connected a plurality of mobile side AC/DC converters. According to a first alternative of the present invention output terminal pairs of the plurality of mobile side AC/DC converters are connected in series. According to a second alternative of the present invention output terminal pairs of the plurality of mobile side AC/DC converters are connected in parallel.

Abstract: A cascode switch comprising a normally-on semiconductor device comprising a gate, a source and a drain, and a normally-off semiconductor device comprising a gate, a source and a drain. The drain of the normally-off semiconductor device coupled to the normally-on semiconductor device, the source of the normally-on semiconductor device coupled to the drain of the normally-off semiconductor device and the gate of the normally-on semiconductor device coupled to the source of the normally-off semiconductor device. The cascode switch further comprises a leakage current clamp coupled across the normally-off semiconductor device, the leakage current clamp circuit configured to prevent the drain of the normally-off semiconductor from going too high due to leakage current.

Abstract: Efficient measures to improve electrical performance in a mobile side output circuitry of a wireless power transmission system are provided. The mobile side circuitry of the wireless power transmission system has a mobile side transformer stage comprising at least one primary side winding and a plurality of secondary side windings. To the plurality of secondary side windings there are connected a plurality of mobile side AC/DC converters. According to a first alternative of the present invention output terminal pairs of the plurality of mobile side AC/DC converters are connected in series. According to a second alternative of the present invention output terminal pairs of the plurality of mobile side AC/DC converters are connected in parallel.

Abstract: A cascode switch comprising a normally-on semiconductor device comprising a gate, a source and a drain, and a normally-off semiconductor device comprising a gate, a source and a drain. The drain of the normally-off semiconductor device coupled to the normally-on semiconductor device, the source of the normally-on semiconductor device coupled to the drain of the normally-off semiconductor device and the gate of the normally-on semiconductor device coupled to the source of the normally-off semiconductor device. The cascode switch further comprises a leakage current clamp coupled across the normally-off semiconductor device, the leakage current clamp circuit configured to prevent the drain of the normally-off semiconductor from going too high due to leakage current.

Abstract: A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor comprises an array of a plurality of islands, each island comprising an active region, source and drain electrodes, and a gate electrode. Electrodes of each island are electrically isolated from electrodes of neighboring islands in at least one direction of the array. Source, drain and gate contact pads are provided to enable electrical testing of each island. After electrical testing of islands to identify defective islands, overlying electrical connections are formed to interconnect source electrodes in parallel, drain electrodes in parallel, and to interconnect gate electrodes to form a common gate electrode of large gate width Wg. Interconnections are provided selectively to good islands, while electrically isolating defective islands. This approach makes it economically feasible to fabricate large area GaN devices, including hybrid devices.

Abstract: Switches comprising a normally-off semiconductor device and a normally-on semiconductor device in cascode arrangement are described. The switches include a capacitor connected between the gate of the normally-on device and the source of the normally-off device. The switches may also include a zener diode connected in parallel with the capacitor between the gate of the normally-on device and the source of the normally-off device. The switches may also include a pair of zener diodes in series opposing arrangement between the gate and source of the normally-off device. Switches comprising multiple normally-on and/or multiple normally-off devices are also described. The normally-on device can be a JFET such as a SiC JFET. The normally-off device can be a MOSFET such as a Si MOSFET. The normally-on device can be a high voltage device and the normally-off device can be a low voltage device. Circuits comprising the switches are also described.

Abstract: A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor comprises an array of a plurality of islands, each island comprising an active region, source and drain electrodes, and a gate electrode. Electrodes of each island are electrically isolated from electrodes of neighbouring islands in at least one direction of the array. Source, drain and gate contact pads are provided to enable electrical testing of each island. After electrical testing of islands to identify defective islands, overlying electrical connections are formed to interconnect source electrodes in parallel, drain electrodes in parallel, and to interconnect gate electrodes to form a common gate electrode of large gate width Wg. Interconnections are provided selectively to good islands, while electrically isolating defective islands. This approach makes it economically feasible to fabricate large area GaN devices, including hybrid devices.

Abstract: In an AC-AC converter comprising a primary side, a secondary side and a regulator, wherein the regulator comprises a voltage regulation circuit configured to determine an error voltage based on an at least partially alternating feedback voltage fed into the regulator from the secondary side of the AC-AC converter and to supply this error voltage and/or an information about this error voltage to the primary side of the AC-AC converter, the regulator comprises an averaging circuit configured to determine an average DC voltage based on the feedback voltage.

Abstract: A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor comprises an array of a plurality of islands, each island comprising an active region, source and drain electrodes, and a gate electrode. Electrodes of each island are electrically isolated from electrodes of neighboring islands in at least one direction of the array. Source, drain and gate contact pads are provided to enable electrical testing of each island. After electrical testing of islands to identify defective islands, overlying electrical connections are formed to interconnect source electrodes in parallel, drain electrodes in parallel, and to interconnect gate electrodes to form a common gate electrode of large gate width Wg. Interconnections are provided selectively to good islands, while electrically isolating defective islands. This approach makes it economically feasible to fabricate large area GaN devices, including hybrid devices.

Abstract: A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor comprises an array of a plurality of islands, each island comprising an active region, source and drain electrodes, and a gate electrode. Electrodes of each island are electrically isolated from electrodes of neighboring islands in at least one direction of the array. Source, drain and gate contact pads are provided to enable electrical testing of each island. After electrical testing of islands to identify defective islands, overlying electrical connections are formed to interconnect source electrodes in parallel, drain electrodes in parallel, and to interconnect gate electrodes to form a common gate electrode of large gate width Wg. Interconnections are provided selectively to good islands, while electrically isolating defective islands. This approach makes it economically feasible to fabricate large area GaN devices, including hybrid devices.

Abstract: A voltage limiter for power components includes: a unipolar primary transistor, including a drain terminal connected to an input of the voltage limiter, a source terminal connected to an output of the voltage limiter, and a gate terminal connected to a predetermined potential. The gate terminal connected to the predetermined potential is configured to limit an input voltage signal at the drain terminal to a predetermined maximum value at the source terminal.

Abstract: In an AC-AC converter comprising a primary side, a secondary side and a regulator, wherein the regulator comprises a voltage regulation circuit configured to determine an error voltage based on an at least partially alternating feedback voltage fed into the regulator from the secondary side of the AC-AC converter and to supply this error voltage and/or an information about this error voltage to the primary side of the AC-AC converter, the regulator comprises an averaging circuit configured to determine an average DC voltage based on the feedback voltage.

Abstract: Switches comprising a normally-off semiconductor device and a normally-on semiconductor device in cascode arrangement are described. The switches include a capacitor connected between the gate of the normally-on device and the source of the normally-off device. The switches may also include a zener diode connected in parallel with the capacitor between the gate of the normally-on device and the source of the normally-off device. The switches may also include a pair of zener diodes in series opposing arrangement between the gate and source of the normally-off device. Switches comprising multiple normally-on and/or multiple normally-off devices are also described. The normally-on device can be a JFET such as a SiC JFET. The normally-off device can be a MOSFET such as a Si MOSFET. The normally-on device can be a high voltage device and the normally-off device can be a low voltage device. Circuits comprising the switches are also described.

Abstract: A magnetic device to be surface mounted on a substantially planar thermally conductive surface comprises a circuit board containing a winding pattern having at least one winding and a magnetic core that is at least partially encompassing the winding pattern. On a bottom side of the circuit board a region corresponding to a substantial part of the winding pattern is covered by a thermally conductive material for thermally contacting the thermally conductive surface. A transformer arrangement comprises such a magnetic device as well as a thermally clad circuit board having a surface area covered by a thermally conductive material, corresponding to at least substantially the covered region on the bottom side of the circuit board. For assembly, the covered region on the bottom side of the circuit board is soldered to the covered region on the surface of the thermally clad circuit board.

Abstract: A magnetic device to be surface mounted on a substantially planar thermally conductive surface comprises a circuit board containing a winding pattern having at least one winding and a magnetic core that is at least partially encompassing the winding pattern. On a bottom side of the circuit board a region corresponding to a substantial part of the winding pattern is covered by a thermally conductive material for thermally contacting the thermally conductive surface. A transformer arrangement comprises such a magnetic device as well as a thermally clad circuit board having a surface area covered by a thermally conductive material, corresponding to at least substantially the covered region on the bottom side of the circuit board. For assembly, the covered region on the bottom side of the circuit board is soldered to the covered region on the surface of the thermally clad circuit board.

Abstract: A power transformer for a power converter includes a magnetic core, a primary winding and two serially connected secondary windings. In order to sense the output current to generate therefrom a control signal for controlling a switching of the synchronous rectifiers of the power converter, the power transformer includes an integrated current transformer with a ring-type core and a secondary winding. The primary windings of the current transformer are formed by the end portions of the secondary windings that are fed through the ring-type core. Accordingly, the end portions form a turn of the secondary windings of the main transformer as well as a turn of the primary winding of the current transformer. Accordingly, only one current transformer is needed, which means lower costs and less space required, and the losses due to the wiring to and from the current transformer can be eliminated.

Abstract: With direct current/direct current converters of modern construction, which can be operated at frequencies as high as 500 kHz, the number of secondary windings that are necessary decreases with simultaneously high currents, so the necessary voltage can be generated by a single winding, or even by less than one winding. A push-pull converter exhibits, for example, a transformer with a center limb (19) and two outer limbs, and that contains on the secondary side two coils (29, 30), each of which consists of a single, complete winding with one center tap (B, E) each. These coils are placed around the center limb (19) in such a way that the two center taps (B, E) come to be located opposite each other in two openings (18) between the outer limbs.