Patents by Inventor Nigel Terence Poole

Nigel Terence Poole has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10157443
    Abstract: The techniques of this disclosure include deferred batching of incremental constant loads. Graphics APIs include the ability to use lightweight constants for use by shaders. A buffer is allocated by a graphics processing unit (GPU) driver that contains a snapshot of the current lightweight constants. This may provide a complete set of state to serve as a starting point. From then on updates to the lightweight constants may be appended to this buffer in an incremental fashion by inserting the update and increasing the size of the buffer by a command processor on a graphics processing unit (GPU). The incremental nature of the updates may be captured, but removes the need for issuing them on every draw call and instead the incremental updates may be batch processed when a live draw call is encountered.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: December 18, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Richard Hammerstone, Thomas Edwin Frisinger, Andrew Evan Gruber, Nigel Terence Poole
  • Patent number: 10134103
    Abstract: A method of data processing, the method comprising receiving, at a graphics processing unit (GPU), a command stream, the command stream including one or more commands to be performed by the GPU and at least one command stream marker, the at least one command stream marker indicating a workload type of the command stream, determining, by the GPU, an operation algorithm for the GPU based on the at least one command stream marker prior to executing the command stream, and executing, by the GPU, the command stream based on the operation algorithm.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: November 20, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Anirudh Rajendra Acharya, David Rigel Garcia Garcia, Nigel Terence Poole
  • Patent number: 10002021
    Abstract: This disclosure is directed to deferred preemption techniques for scheduling graphics processing unit (GPU) command streams for execution on a GPU. A host CPU is described that is configured to control a GPU to perform deferred-preemption scheduling. For example, a host CPU may select one or more locations in a GPU command stream as being one or more locations at which preemption is allowed to occur in response to receiving a preemption notification, and may place one or more tokens in the GPU command stream based on the selected one or more locations. The tokens may indicate to the GPU that preemption is allowed to occur at the selected one or more locations. This disclosure further describes a GPU configured to preempt execution of a GPU command stream based on one or more tokens placed in a GPU command stream.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: June 19, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Eduardus A Metz, Nigel Terence Poole, Colin Christopher Sharp, Andrew Gruber
  • Publication number: 20170116701
    Abstract: A method of data processing, the method comprising receiving, at a graphics processing unit (GPU), a command stream, the command stream including one or more commands to be performed by the GPU and at least one command stream marker, the at least one command stream marker indicating a workload type of the command stream, determining, by the GPU, an operation algorithm for the GPU based on the at least one command stream marker prior to executing the command stream, and executing, by the GPU, the command stream based on the operation algorithm.
    Type: Application
    Filed: March 29, 2016
    Publication date: April 27, 2017
    Inventors: Anirudh Rajendra Acharya, David Rigel Garcia Garcia, Nigel Terence Poole
  • Patent number: 9589314
    Abstract: Systems, methods, and apparatus for performing queries in a graphics processing system are disclosed. These systems, methods, and apparatus may be configured to read a running counter at the start of the query to determine a start value, wherein the running counter counts discrete graphical entities, read the running counter at the end of the query to determine an end value, and subtract the start value from the end value to determine a result.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: March 7, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Avinash Seetharamaiah, Hitendra Mohan Gangani, Nigel Terence Poole
  • Publication number: 20140320512
    Abstract: Systems, methods, and apparatus for performing queries in a graphics processing system are disclosed. These systems, methods, and apparatus may be configured to read a running counter at the start of the query to determine a start value, wherein the running counter counts discrete graphical entities, read the running counter at the end of the query to determine an end value, and subtract the start value from the end value to determine a result.
    Type: Application
    Filed: August 29, 2013
    Publication date: October 30, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Avinash Seetharamaiah, Hitendra Mohan Gangani, Nigel Terence Poole
  • Publication number: 20140022266
    Abstract: This disclosure is directed to deferred preemption techniques for scheduling graphics processing unit (GPU) command streams for execution on a GPU. A host CPU is described that is configured to control a GPU to perform deferred-preemption scheduling. For example, a host CPU may select one or more locations in a GPU command stream as being one or more locations at which preemption is allowed to occur in response to receiving a preemption notification, and may place one or more tokens in the GPU command stream based on the selected one or more locations. The tokens may indicate to the GPU that preemption is allowed to occur at the selected one or more locations. This disclosure further describes a GPU configured to preempt execution of a GPU command stream based on one or more tokens placed in a GPU command stream.
    Type: Application
    Filed: July 20, 2012
    Publication date: January 23, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Eduardus A Metz, Nigel Terence Poole, Colin Christopher Sharp, Andrew Gruber