Abstract: A bias block for providing a bias voltage includes a transistor having a control terminal, a first current terminal and a second current terminal. A voltage level at the control terminal determines a magnitude of current flowing between the first current terminal and the second current terminal. The first current terminal is coupled to a supply voltage via a first impedance and the second current terminal is coupled to a constant reference potential via a second impedance. The second current terminal provides the bias voltage. The bias block further includes a capacitor coupled between the control terminal and the second current terminal of the transistor.

Abstract: A device includes a first oscillator, a second oscillator and a frequency comparison block. The first oscillator includes a first LC tank circuit and is designed to generate first sustained oscillations at a first resonant frequency. The second oscillator includes a second LC tank circuit and is designed to generate second sustained oscillations at a second resonant frequency. The frequency comparison block is designed to perform a comparison of the frequencies of the second sustained oscillations and the first sustained oscillations to determine a change in inductance in one of a first inductor of the first LC tank circuit and a second inductor of the second LC tank circuit. One of the oscillators serves as a reference oscillator, and enables determination of the change in inductance to be immune to changes in environmental conditions.

Abstract: A device includes a first oscillator, a second oscillator and a frequency comparison block. The first oscillator includes a first LC tank circuit and is designed to generate first sustained oscillations at a first resonant frequency. The second oscillator includes a second LC tank circuit and is designed to generate second sustained oscillations at a second resonant frequency. The frequency comparison block is designed to perform a comparison of the frequencies of the second sustained oscillations and the first sustained oscillations to determine a change in inductance in one of a first inductor of the first LC tank circuit and a second inductor of the second LC tank circuit. One of the oscillators serves as a reference oscillator, and enables determination of the change in inductance to be immune to changes in environmental conditions.

Abstract: A frequency divider includes a set of frequency-dividing units coupled in series in a sequential order, with the sequence of frequency-dividing units including a lowest unit and a highest unit, with the remaining units being disposed in series between the lowest unit and the highest unit. The lowest unit is coupled to receive an input clock whose frequency is to be divided and provided as an output clock. Each frequency-dividing unit in the set is coupled to receive a corresponding first clock as an input and is operable to generate a corresponding second clock as an output. The frequency divider includes a logic block to generate a first set of edges of the output clock synchronous with the input clock. The logic block is designed to generate a second set of edges of the output clock synchronous with the output clock of a highest operative frequency-dividing unit in the set.

Abstract: A frequency divider includes a set of frequency-dividing units coupled in series in a sequential order, with the sequence of frequency-dividing units including a lowest unit and a highest unit, with the remaining units being disposed in series between the lowest unit and the highest unit. The lowest unit is coupled to receive an input clock whose frequency is to be divided and provided as an output clock. Each frequency-dividing unit in the set is coupled to receive a corresponding first clock as an input and is operable to generate a corresponding second clock as an output. The frequency divider includes a logic block to generate a first set of edges of the output clock synchronous with the input clock. The logic block is designed to generate a second set of edges of the output clock synchronous with the output clock of a highest operative frequency-dividing unit in the set.