Abstract: An integrated circuit is provided that includes compression or decompression circuitry along a datapath. An integrated circuit system may include first memory to store data, data utilization circuitry to operate on the data, and a configurable data distribution path to transfer data between the first memory and the data utilization circuitry. Compression or decompression circuitry may be disposed along the data distribution path between the first memory and the data utilization circuitry to enable the first memory to store the data in compressed form and to enable the data utilization circuitry to operate on the data in uncompressed form. The compression or decompression circuitry may use lossless sparse encoding, lossless multi-precision encoding, lossless prefix lookup table-based encoding, Huffman encoding, selective compression, or lossy compression.

Abstract: This disclosure is directed to a digital signal processing (DSP) block that includes multiple weight registers configurable to receive and store a first plurality of values having multiple precisions, and multiple multipliers that are each configurable to receive a respective value of the first plurality of values. The DSP block further includes one or more inputs configurable to receive a second plurality of values, and a multiplexer network configurable to receive the second plurality of values and route each respective value of the second plurality of values to a multiplier of the multipliers. The multipliers are configurable to simultaneously multiply each value of the first plurality of values by a respective value of the second plurality of values to generate a plurality of products. Additionally, the DSP block includes adder circuitry configurable to generate a first sum and a second sum based on the plurality of products.

Abstract: This disclosure is directed to a digital signal processing (DSP) block that includes multiple weight registers configurable to receive and store a first plurality of values, and multiple multipliers that are each configurable to receive a respective value of the first plurality of values. The DSP block further includes one or more inputs configurable to receive a second plurality of values, and a multiplexer network configurable to receive the second plurality of values and route each respective value of the second plurality of values to a multiplier of the multipliers. The multipliers are configurable to simultaneously multiply each value of the first plurality of values by a respective value of the second plurality of values to generate a plurality of products. Additionally, the DSP block includes adder circuitry configurable to generate a first sum and a second sum based on the plurality of products.