Patents by Inventor Niichi Itoh
Niichi Itoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7394115Abstract: A clock signal transmission line in the semiconductor integrated circuit device includes a plurality of straight portions arranged side by side in a predetermined direction and a plurality of bent portions connecting the respective straight portions. At least two of a plurality of signal lines to which a clock signal is transmitted are connected to different straight portions. Consequently, a semiconductor integrated circuit device which can reduce a clock skew when transmitting a clock signal to a plurality of signal lines is provided.Type: GrantFiled: January 20, 2006Date of Patent: July 1, 2008Assignee: Renesas Technology Corp.Inventor: Niichi Itoh
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Publication number: 20060123372Abstract: A clock signal transmission line in the semiconductor integrated circuit device includes a plurality of straight portions arranged side by side in a predetermined direction and a plurality of bent portions connecting the respective straight portions. At least two of a plurality of signal lines to which a clock signal is transmitted are connected to different straight portions. Consequently, a semiconductor integrated circuit device which can reduce a clock skew when transmitting a clock signal to a plurality of signal lines is provided.Type: ApplicationFiled: January 20, 2006Publication date: June 8, 2006Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Niichi Itoh
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Patent number: 7026667Abstract: A clock signal transmission line in the semiconductor integrated circuit device includes a plurality of straight portions arranged side by side in a predetermined direction and a plurality of bent portions connecting the respective straight portions. At least two of a plurality of signal lines to which a clock signal is transmitted are connected to different straight portions. Consequently, a semiconductor integrated circuit device which can reduce a clock skew when transmitting a clock signal to a plurality of signal lines is provided.Type: GrantFiled: August 23, 2002Date of Patent: April 11, 2006Assignee: Renesas Technology Corp.Inventor: Niichi Itoh
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Publication number: 20050246407Abstract: A multiplication array is divided into divided Wallace tree arrays each performing multiplication by addition in a tree-like form. An addition result is transmitted from the divided Wallace tree arrays to a final addition circuit. Thus, an interconnection line length of a critical path of a multiplication apparatus can be reduced.Type: ApplicationFiled: July 6, 2005Publication date: November 3, 2005Applicant: Renesas Technology Corp.Inventor: Niichi Itoh
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Publication number: 20050138102Abstract: An arithmetic unit is provided which is capable of enhancing area efficiency while suppressing operating speed reduction. A third partial product adder (T101) is divided into a high order part (T101a) including high-order 12 bits and a low order part (T101b) including low-order 33 bits. The high order part (T101a) and the low order part (T101b) are placed in different rows in a Wallace tree array. Particularly, the low order part (T101b) is placed in a middle row in the Wallace tree array. More specifically, the low order part (T101b) is placed right under a high order part (S101a) and right above a low order part (S102b). The high order part (T101a) is placed in the bottom row of the Wallace tree array. More specifically, the high order part (T101a) is placed right under a high order part (S102a).Type: ApplicationFiled: November 17, 2004Publication date: June 23, 2005Applicant: Renesas Technology Corp.Inventor: Niichi Itoh
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Patent number: 6856170Abstract: A clock generator (10a) outputs either a first clock signal or a second clock signal. The second clock signal is higher in frequency than the first clock signal. Under control of a control signal (CNTL1), when the first clock signal and the second clock signal are outputted from the clock generator (10a), a selector (81a) transmits the first and second clock signals to a clock transmission line (42) and to a clock transmission line (41), respectively. The clock transmission line (41) is greater in linewidth than the clock transmission line (42). Under control of the control signal (CNTL1), a selector (82a) connects either the clock transmission line (41) or the clock transmission line (42) to the outside.Type: GrantFiled: May 21, 2003Date of Patent: February 15, 2005Assignee: Renesas Technology Corp.Inventor: Niichi Itoh
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Patent number: 6838770Abstract: A semiconductor device is provided with dummy patterns at an originally thinner portion of each of layers, and each of these dummy patterns is electrically connected to a reference wire that is either a power-supply wire or a ground wire.Type: GrantFiled: June 27, 2001Date of Patent: January 4, 2005Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Niichi Itoh
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Publication number: 20040095165Abstract: A clock generator (10a) outputs either a first clock signal or a second clock signal. The second clock signal is higher in frequency than the first clock signal. Under control of a control signal (CNTL1), when the first clock signal and the second clock signal are outputted from the clock generator (10a), a selector (81a) transmits the first and second clock signals to a clock transmission line (42) and to a clock transmission line (41), respectively. The clock transmission line (41) is greater in linewidth than the clock transmission line (42). Under control of the control signal (CNTL1), a selector (82a) connects either the clock transmission line (41) or the clock transmission line (42) to the outside.Type: ApplicationFiled: May 21, 2003Publication date: May 20, 2004Applicant: Renesas Technology Corp.Inventor: Niichi Itoh
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Publication number: 20030063697Abstract: A clock signal transmission line in the semiconductor integrated circuit device includes a plurality of straight portions arranged side by side in a predetermined direction and a plurality of bent portions connecting the respective straight portions. At least two of a plurality of signal lines to which a clock signal is transmitted are connected to different straight portions. Consequently, a semiconductor integrated circuit device which can reduce a clock skew when transmitting a clock signal to a plurality of signal lines is provided.Type: ApplicationFiled: August 23, 2002Publication date: April 3, 2003Applicant: Mitsubishi denki Kabushiki KaishaInventor: Niichi Itoh
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Publication number: 20020024148Abstract: A semiconductor device is provided with dummy patterns at an originally thinner portion of each of layers, and each of these dummy patterns is electrically connected to a reference wire that is either a power-supply wire or a ground wire.Type: ApplicationFiled: June 27, 2001Publication date: February 28, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Niichi Itoh
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Patent number: 6327166Abstract: Provided is a semiconductor memory having a layout structure in which a memory cell has excellent patterning controllability. A pattern of element components (active regions 10 to 15 and 21 to 23 and polysilicon regions 31 to 42) of a memory cell for one memory cell unit of a memory cell array region 1 is identical to that of a dummy cell of a peripheral dummy cell region 3, and both patterns present a line symmetrical relationship with respect to a boundary line BC1. In addition, a pattern of the memory cell for one memory cell unit of the memory cell array region 1 is identical to that of a dummy cell of a power wiring region 2, and both patterns present a line symmetrical relationship with respect to a boundary line BC2.Type: GrantFiled: August 31, 2000Date of Patent: December 4, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Niichi Itoh, Yasunobu Nakase, Tetsuya Watanabe, Chikayoshi Morishima
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Patent number: 6317865Abstract: A wiring-capacitance improvement aid device aiding in eliminating a capacitance-attributable error of layout data generated by an automatic arrangement and routing tool includes a subject-net extraction portion extracting a subject net with a capacitance-attributable error, a network rip-up portion ripping up a cell netted within a predetermined range with respect to a subject net extracted by the subject-net extraction portion, and a constraint imposition portion imposing a wiring-capacitance constraint on a net connected to a cell ripped up by the network rip-up portion.Type: GrantFiled: March 24, 1999Date of Patent: November 13, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Niichi Itoh
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Publication number: 20010009012Abstract: A multiplication array is divided into divided Wallace tree arrays each performing multiplication by addition in a tree-like form. An addition result is transmitted from the divided Wallace tree arrays to a final addition circuit. Thus, an interconnection line length of a critical path of a multiplication apparatus can be reduced.Type: ApplicationFiled: January 9, 2001Publication date: July 19, 2001Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Niichi Itoh
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Patent number: 6201758Abstract: A precharge circuit and a bit line load circuit are provided to a read bit line pair. The bit line load circuit continuously supplies a prescribed current to a read bit line. When data is written to one of memory cells selected in common by one read word line, the level of each read bit line will not be lowered to the level of the ground potential by the bit line load circuit if a read word line is activated, and therefore the loads of both discharge and charge operations by transistors in the memory cell are reduced.Type: GrantFiled: February 7, 2000Date of Patent: March 13, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Chikayoshi Morishima, Yasunobu Nakase, Tetsuya Watanabe, Niichi Itoh
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Patent number: 6128208Abstract: Provided is a semiconductor memory having a layout structure in which a memory cell has excellent patterning controllability. A pattern of element components (active regions 10 to 15 and 21 to 23 and polysilicon regions 31 to 42) of a memory cell for one memory cell unit of a memory cell array region 1 is identical to that of a dummy cell of a peripheral dummy cell region 3, and both patterns present a line symmetrical relationship with respect to a boundary line BC1. In addition, a pattern of the memory cell for one memory cell unit of the memory cell array region 1 is identical to that of a dummy cell of a power wiring region 2, and both patterns present a line symmetrical relationship with respect to a boundary line BC2.Type: GrantFiled: September 23, 1999Date of Patent: October 3, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Niichi Itoh, Yasunobu Nakase, Tetsuya Watanabe, Chikayoshi Morishima