Abstract: A computer system is provided for protecting a circuit design for an application specific integrated circuit. The computer system includes a logic circuit replacement tool for identifying a module of logic circuitry for replacement in at least a portion of the circuit design. The logic circuit replacement tool generates a transformed circuit design for the application specific integrated circuit by replacing the logic circuitry in the module with a configurable circuit that performs a logic function of the logic circuitry when a bitstream stored in storage circuits in the configurable circuit configures the configurable circuit. The transformed circuit design includes the configurable circuit in the module.

Abstract: Methods and systems are provided for protecting a circuit design for an integrated circuit. Logic circuits are identified in at least a portion of the circuit design for replacement. The logic circuits in the circuit design are replaced with a bitstream and configurable circuits that comprise memory circuits. A transformed circuit design is generated for the integrated circuit that comprises the configurable circuits. The configurable circuits in the transformed circuit design perform logic functions of the logic circuits when the bitstream is stored in the memory circuits in the configurable circuits.

Abstract: Methods and systems are provided for protecting a circuit design for an integrated circuit. Logic circuits are identified in at least a portion of the circuit design for replacement. The logic circuits in the circuit design are replaced with a bitstream and configurable circuits that comprise memory circuits. A transformed circuit design is generated for the integrated circuit that comprises the configurable circuits. The configurable circuits in the transformed circuit design perform logic functions of the logic circuits when the bitstream is stored in the memory circuits in the configurable circuits.

Abstract: Systems or methods of the present disclosure may provide a computing system that includes a processor and one or more implemented designs in one or more configurable circuits of a programmable logic fabric. The computing system also includes a memory coupled to the programmable logic fabric. The computing system further includes an accelerator that is located in-line between the one or more configurable circuits and the memory. The accelerator is defined using a low-level programming language. The processor is coupled to the accelerator and is configured to enable modification of the definition of the accelerator by converting a high-level programming language to the low-level programming language to change the way that the accelerator operates.

Abstract: A programmable logic circuit is disclosed that includes a latch for enhancing the circuit logic capacity. In a multiplier configuration, the circuit comprises a logic block; and a latch having a latch output coupled to a logic block input, wherein the latch output computes an AND function of a first and second latch input.

Abstract: A computational unit is disclosed to increment or decrement n-bits of data. The unit has n/3 logic blocks to process the n-bits of data, each logic block including: first and second multiplexers to propagate a carry chain; and first, second and third exclusive-OR (XOR) circuits coupled to the carry chain of the multiplexers to generate a 3-bit incremented output.

Abstract: Method, apparatus, and computer readable medium for circuit design for a programmable device is described. In one example, a logical description of a circuit design having static logic and reconfigurable logic is imported into a graphical environment. The circuit design is processed in the graphical environment. In particular, the logical description is floorplanned to locate the static logic and the reconfigurable logic in a floorplan of the programmable device. At least one design rule check (DRC) is performed. A partial reconfiguration implementation of the circuit design is then managed for the programmable device.

Abstract: A logic circuit is disclosed that includes a latch for enhancing the circuit logic capacity. The circuit includes a logic block comprising a plurality of logic inputs and at least one logic output, the logic output generating a logic function of the plurality of logic inputs; a first latch input to provide a data state to store in the latch is coupled to said at least one output of logic block; a global latch input to change the stored data state of the latch couple by a programmable method to a local input; and a latch output, wherein when the local input is coupled to the global latch input, the latch output generates logic function of the logic output and the local input.

Abstract: A computational unit is disclosed to increment or decrement n-bits of data. The unit has n/3 logic blocks to process the n-bits of data, each logic block including: first and second multiplexers to propagate a carry chain; and first, second and third exclusive—OR (XOR) circuits coupled to the carry chain of the multiplexers to generate a 3-bit incremented output.

Abstract: A latch is described, comprising: a first programmable logic element (LE); and a second programmable logic element (LE); and an output of the first LE adapted to directly couple to a first input of the second LE; and an output of the second LE coupled to a first input of the first LE; and a first common input coupled to a second input of the first and second LE; and a second common input coupled to a third input of the first and second LE.

Abstract: Disclosed is a programmable logic device adapted to implement a shift register, the device comprising: a logic block comprised of: a latch having an input; and a logic element having an output capable of coupling to an adjacent logic block and the latch input, wherein the output is coupled to the adjacent logic block and decoupled from the latch input; and an interconnect coupled to the latch and adapted to transmit the latch output to an input of the logic element. In the device, the logic element is configured as a route through for the latch output to couple to the adjacent logic block.

Abstract: A latch is described, comprising: a first programmable logic element (LE); and a second programmable logic element (LE); and an output of the first LE adapted to directly couple to a first input of the second LE; and an output of the second LE coupled to a first input of the first LE; and a first common input coupled to a second input of the first and second LE; and a second common input coupled to a third input of the first and second LE.

Abstract: Disclosed is a programmable logic device adapted to implement a shift register, the device comprising: a logic block comprised of: a latch having an input; and a logic element having an output capable of coupling to an adjacent logic block and the latch input, wherein the output is coupled to the adjacent logic block and decoupled from the latch input; and an interconnect coupled to the latch and adapted to transmit the latch output to an input of the logic element. In the device, the logic element is configured as a route through for the latch output to couple to the adjacent logic block.

Abstract: A programmable logic circuit is disclosed that includes a latch for enhancing the circuit logic capacity. In a multiplier configuration, the circuit comprises a logic block; and a latch having a latch output coupled to a logic block input, wherein the latch output computes an AND function of a first and second latch input.

Abstract: A logic circuit is disclosed that includes a latch for enhancing the circuit logic capacity. The circuit includes a logic block comprising a plurality of logic inputs and at least one logic output, the logic output generating a logic function of the plurality of logic inputs; a first latch input to provide a data state to store in the latch is coupled to said at least one output of logic block; a global latch input to change the stored data state of the latch couple by a programmable method to a local input; and a latch output, wherein when the local input is coupled to the global latch input, the latch output generates logic function of the logic output and the local input.