Patents by Inventor Niju Alex Geevarughese

Niju Alex Geevarughese has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Synchronous, internal clock edge alignment for integrated circuit testing
    Patent number: 10128828
    Abstract: A synchronous clock edge alignment system and method increases detection coverage of transition delay faults that occur in logic circuits that have data released by a clock at an input of logic circuits internal to an integrated circuit and/or released at the output of the logic circuits when testing an integrated circuit. To increase detection coverage of inter-clock transition delay faults, in at least one embodiment, the synchronous clock edge alignment system and method align same transition type edges of internal data releasing clock signals, and at least two of the clock signals have different frequencies. By aligning the edges of the clock signals, transition delay faults that might otherwise not have occurred can be detected by, for example, a conventional circuit testing apparatus. Thus, aligning the edges of the clock signals increases detection of inter-clock transition delay faults.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: November 13, 2018
    Assignee: Cirrus Logic, Inc.
    Inventors: Muraleedharan Ramakrishnan, Bhoodev Kumar, Vivek Oppula, Niju Alex Geevarughese
  • SYNCHRONOUS, INTERNAL CLOCK EDGE ALIGNMENT FOR INTEGRATED CIRCUIT TESTING
    Publication number: 20170310315
    Abstract: A synchronous clock edge alignment system and method increases detection coverage of transition delay faults that occur in logic circuits that have data released by a clock at an input of logic circuits internal to an integrated circuit and/or released at the output of the logic circuits when testing an integrated circuit. To increase detection coverage of inter-clock transition delay faults, in at least one embodiment, the synchronous clock edge alignment system and method align same transition type edges of internal data releasing clock signals, and at least two of the clock signals have different frequencies. By aligning the edges of the clock signals, transition delay faults that might otherwise not have occurred can be detected by, for example, a conventional circuit testing apparatus. Thus, aligning the edges of the clock signals increases detection of inter-clock transition delay faults.
    Type: Application
    Filed: April 11, 2017
    Publication date: October 26, 2017
    Applicant: Cirrus Logic International Semiconductor, Ltd.
    Inventors: Muraleedharan Ramakrishnan, Bhoodev Kumar, Vivek Oppula, Niju Alex Geevarughese