Abstract: A mechanism is disclosed for implementing an interpreter with hierarchical execution loops. In one embodiment, the interpreter has a slow processing loop and a fast processing loop. In one embodiment, the slow processing loop comprises resources for executing infrequently executed instructions and instructions with relatively complicated implementations, and the fast processing loop comprises resources for executing frequently executed instructions and instructions with relatively simple implementations. Instructions are mostly executed in the fast processing loop. Only if an instruction is not supported by the fast processing loop will it be executed in the slow processing loop. Implementing the interpreter in this manner improves cache utilization and makes it easier for a compiler to generate more optimal code for the interpreter, thereby resulting in considerably faster execution times.

Abstract: One embodiment of the present invention provides a method for increasing performance of code executing on a platform-independent virtual machine. The method operates by receiving a request to resolve an entry in a symbol table at run-time, wherein resolving the entry requires multiple lookups into the symbol table. It next determines if the entry has previously been resolved. If so, the system returns a direct pointer to a runtime structure associated with the entry, which was returned during a previous resolution of the entry. If not, the system resolves the entry through multiple lookups into the symbol table to produce a direct pointer to the runtime structure, and replaces the entry with the direct pointer. In a variation on the above embodiment, the symbol table assumes the form of a constant pool within an object-oriented class file defined within the JAVA programming language.

Abstract: A method, system and apparatus for generating and optimizing native code in a runtime compiler from a group of bytecodes presented to the compiler. The compiler accesses information that indicates a likelihood that a class will be a particular type when accessed by the running program. Using the accessed information, the compiler selects a code generation method from a plurality of code generation methods. A code generator generates optimized native code according to the selected code generation method and stores the optimized native code in a code cache for reuse.

Abstract: A computer system and a method for operating a processor including the steps of establishing a first register save area and a second register save area in a memory, where each register save area holds data values that define a context. The first context is loaded in the processor by loading at least some of the data values from the first register save area into the plurality of registers. A first pointer value to the first register save area is stored in a current RFSA register. A context switch is indicated by storing a second pointer to the second register save area in the current RFSA register. The first pointer is transferred from the current RFSA register to a previous RFSA register. All of the data values that define the first context are transferred from the registers to a shadow register file. The second context is established in the processor by loading selected data values from the second register file save area into the plurality of registers.

Abstract: A method, system, and computer program product for synchronized thread execution in a multithreaded processor are described. Each synchronized thread refers to at least one object identified by an object identification (OID) that is shared among a plurality of synchronized threads. One of the synchronized threads is selected for execution. Upon entering the selected thread, an entry sequence indicates that the shared object should be locked by pushing its OID onto a lock stack. The operations defined by the selected thread are executed and the indication is removed by pushing the OID from the lock stack.

Abstract: The present invention provides a method and an apparatus for translating a virtual address to a physical address in a computer system. The system receives a virtual address during an execution or a fetch of a program instruction. The system determines if the virtual address is in an upper portion or a lower portion of a virtual address space. If the virtual address is in the lower portion of the virtual address space, the system adds the virtual address to a first base address to produce the physical address. The system also compares the virtual address against an upper bound. If the virtual address has a larger value than the upper bound, the system indicates an illegal access. If the virtual address is in the upper portion of the virtual address space, the system adds the virtual address to a second base address to produce the physical address. The system also compares the virtual address against a lower bound.

Abstract: A system is provided for storing data for a plurality of host computers on a plurality of storage arrays so that data on each storage array can be accessed by any host computer. A plurality of adapter cards are used. Each adapter has controller functions for a designated storage array. There is an adapter communication interface (interconnect) between all of the adapters in the system. There is also a host application interface between an application program running in the host computer and an adapter. When a data request is made by an application program to a first adapter through a host application interface for data that is stored in a storage array not primarily controlled by the first adapter, the data request is communicated through the adapter communication interface to the adapter primarily controlling the storage array in which the requested data is stored.