Patents by Inventor Nikhil ARORA

Nikhil ARORA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11721402
    Abstract: Storage devices are capable of utilizing failed bit count (FBC) reduction devices to reduce FBCs for word lines in blocks. An FBC reduction device may include a FBC count component, a threshold component, a pre-verify component, and a soft program component. The FBC count component may access the FBC for the word line, where the block has unprogrammed word lines in an unprogrammed region separated from programmed word lines of a programmed region by the word line. The threshold component may determine whether the FBC of the word line exceeds a predetermined threshold. When the FBC exceeds the threshold, the pre-verify component may perform pre-verify operations on the programmed region. The soft program component may program the word line with first data equal to second data programmed in a second block. In response to disabling pre-verify operations, the program component may program the unprogrammed word lines in the unprogrammed region.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: August 8, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amiya Banerjee, Vinayak Bhat, Nikhil Arora
  • Patent number: 11651821
    Abstract: A data storage device includes a controller coupled to one or more memory devices. The controller is configured to determine one or more first wordlines within the memory device that needs more than one pulse for programming and one or more second wordlines within the memory device that needs one pulse and no program verify. The locations of the one or more first wordlines and the one or more second wordlines are stored in a data structure of the memory device. During program operations, the controller utilizes the data structure to determine whether the one or more wordlines being programmed requires only one pulse and no program verify or a multi-loop program. The data structure is updated after an EPWR and/or XOR parity operation.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: May 16, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Nikhil Arora, Lovleen Arora
  • Publication number: 20220343663
    Abstract: A method and system for performing on-device image to text conversion are provided. Embodiments herein relates to the field of performing image to text conversion and more particularly to performing on-device image to text conversion with an improved accuracy. A method performing on-device image to text conversion is provided. The method includes language detection from an image, understanding of text in an edited image and using a contextual and localized lexicon set for post optical character recognition (OCR) correction.
    Type: Application
    Filed: July 7, 2022
    Publication date: October 27, 2022
    Inventors: Sukumar MOHARANA, Gopi RAMENA, Rachit S MUNJAL, Manoj GOYAL, Rutika MOHARIR, Nikhil ARORA, Arun D PRABHU, Shubham VATSAL
  • Patent number: 11467744
    Abstract: Aspects of a storage device including a controller are provided which identifies a bad, open block that causes subsequent erase operations to fail in closed blocks due to charge leakage following a previous program operation in the open block. Each time the controller programs an open block, the controller attempts to erase a plurality of closed blocks following each programming of the open block. When the closed blocks fail to erase, the controller determines whether a number of consecutive erase failures after programming the open block meets a threshold, after which the controller re-attempts to erase the closed blocks. After a successful re-attempt, the controller stores a list of open blocks in memory. In response to repeating these steps a number or plurality of times, the controller stores multiple lists of open blocks in memory, and identifies the single common open block between the multiple lists as a bad block.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: October 11, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Nikhil Arora, Lovleen Arora, Sourabh Sankule, Sameer Hiware
  • Publication number: 20220301645
    Abstract: Storage devices are capable of utilizing failed bit count (FBC) reduction devices to reduce FBCs for word lines in blocks. An FBC reduction device may include a FBC count component, a threshold component, a pre-verify component, and a soft program component. The FBC count component may access the FBC for the word line, where the block has unprogrammed word lines in an unprogrammed region separated from programmed word lines of a programmed region by the word line. The threshold component may determine whether the FBC of the word line exceeds a predetermined threshold. When the FBC exceeds the threshold, the pre-verify component may perform pre-verify operations on the programmed region. The soft program component may program the word line with first data equal to second data programmed in a second block. In response to disabling pre-verify operations, the program component may program the unprogrammed word lines in the unprogrammed region.
    Type: Application
    Filed: June 8, 2022
    Publication date: September 22, 2022
    Inventors: Amiya Banerjee, Vinayak Bhat, Nikhil Arora
  • Publication number: 20220254415
    Abstract: A data storage device includes a controller coupled to one or more memory devices. The controller is configured to determine one or more first wordlines within the memory device that needs more than one pulse for programming and one or more second wordlines within the memory device that needs one pulse and no program verify. The locations of the one or more first wordlines and the one or more second wordlines are stored in a data structure of the memory device. During program operations, the controller utilizes the data structure to determine whether the one or more wordlines being programmed requires only one pulse and no program verify or a multi-loop program. The data structure is updated after an EPWR and/or XOR parity operation.
    Type: Application
    Filed: February 8, 2021
    Publication date: August 11, 2022
    Inventors: Nikhil ARORA, Lovleen ARORA
  • Patent number: 11386969
    Abstract: Storage devices are capable of utilizing failed bit count (FBC) reduction devices to reduce FBCs for word lines in blocks. An FBC reduction device may include a FBC count component, a threshold component, a pre-verify component, and a soft program component. The FBC count component may access the FBC for the word line, where the block has unprogrammed word lines in an unprogrammed region separated from programmed word lines of a programmed region by the word line. The threshold component may determine whether the FBC of the word line exceeds a predetermined threshold. When the FBC exceeds the threshold, the pre-verify component may perform pre-verify operations on the programmed region. The soft program component may program the word line with first data equal to second data programmed in a second block. In response to disabling pre-verify operations, the program component may program the unprogrammed word lines in the unprogrammed region.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: July 12, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amiya Banerjee, Vinayak Bhat, Nikhil Arora
  • Publication number: 20210373764
    Abstract: Aspects of a storage device including a controller are provided which identifies a bad, open block that causes subsequent erase operations to fail in closed blocks due to charge leakage following a previous program operation in the open block. Each time the controller programs an open block, the controller attempts to erase a plurality of closed blocks following each programming of the open block. When the closed blocks fail to erase, the controller determines whether a number of consecutive erase failures after programming the open block meets a threshold, after which the controller re-attempts to erase the closed blocks. After a successful re-attempt, the controller stores a list of open blocks in memory. In response to repeating these steps a number or plurality of times, the controller stores multiple lists of open blocks in memory, and identifies the single common open block between the multiple lists as a bad block.
    Type: Application
    Filed: May 27, 2020
    Publication date: December 2, 2021
    Inventors: Nikhil Arora, Lovleen Arora, Sourabh Sankule, Sameer Hiware
  • Patent number: 11152071
    Abstract: Aspects of a storage device including a controller are provided which recovers misidentified bad blocks that fail to erase due to charge leakage from a previously programmed open block. The controller programs an open block, and attempts to erase a plurality of closed blocks following the programming of the open block. When the closed blocks fail to erase, the controller marks the closed blocks as bad blocks. The controller then determines whether a number of consecutive erase failures after programming the open block meets a threshold, in response to which the controller resets a die including the closed blocks and reattempts to erase the closed blocks. The controller then unmarks as bad blocks the closed blocks which successfully erased in response to the re-attempt.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: October 19, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Nikhil Arora, Lovleen Arora, Sourabh Sankule, Sameer Hiware
  • Publication number: 20110277383
    Abstract: Methods, devices and kits are described for making a growing substrate from recycled coffee grounds and growing mushrooms.
    Type: Application
    Filed: May 10, 2011
    Publication date: November 17, 2011
    Applicant: B.T.T.R. VENTURES LLC
    Inventors: Nikhil ARORA, Alejandro VELEZ
  • Patent number: D704011
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: May 6, 2014
    Inventors: Alejandro Velez, Nikhil Arora