Abstract: A motion adaptive video deinterlacer may process fields of video derived from frames of video. The deinterlacer may use multiple pixel motion engines to provide motion information about the pixels within each field. The output of the motion engines may be used to deinterlace the fields of video based on the detail within a field of video. The deinterlacer may use motion recursion and motion recirculation to provide temporal motion expansion for the pixels within each field. In addition, the deinterlacer may detect various cadences for various regions within the frames of video. The cadences may be detected using a calculated threshold, or without using a calculated threshold.

Abstract: A shared memory video processor including signal processing circuitry. The signal processing circuitry may enable a noise reducer and a de-interlacer to share access to field buffers in a memory device to store various field lines. Some of the stored field lines may also be shared within the signal processing circuitry. The sharing of some stored field lines reduces overall memory bandwidth and capacity requirements. The signal processing circuitry may be capable of performing multiple field line processing. A set of field line buffers may be provided to store field lines for multiple field segments and may provide the data to the corresponding inputs of the signal processing circuitry. To further reduce storage, some of the field line buffers may also be shared among the signal processing circuitry.

Abstract: A scaler positioning module may receive a video signal selected from among a plurality of video signals. The scaler positioning module may include scaler slots for arranging the signal path of the selected video signal through at least one scaler in the scaler positioning module. The scaler slots may enable the scaler positioning module to operate in three modes. The three modes may enable the scaler positioning module to output scaled data without memory operations, scale prior to a memory write, and scale after a memory read. A blank time optimizer (BTO) may receive data from the scaler positioning module at a first clock rate and distributed memory accesses based on a bandwidth requirement determination. The BTO may access memory at a second clock rate. The second clock rate may be slower than the first which may reduce memory bandwidth and enable another video signal to access memory faster.

Abstract: The invention includes a system and the associated method for decoding multiple video signals. The video signals may be component video, composite video or s-video signals each having multiple portions using a multimode video decoder. A selection stage may combine the multiple video signals and select some of their video signal portions for processing. The selection stage may time-multiplex some of the video signal portions. An analog to digital conversion stage may be shared by the time-multiplexing of the video signals. A decoder stage may decode the various signal portions and provide decoded output video signals. These feature may reduce the overall cost of the system. Various clock signals may be used to operate various stages of a multimode video decoder. Some of the clock signals may run at different frequencies and others may operate at a different phase.

Abstract: Disclosed herein are systems and methods for estimating global and local motions between a pair of temporally adjacent frames of an input signal and for applying these motion vectors to produce at least one interpolated, motion-compensated frame between the adjacent frames. In particular, the systems and methods comprise designs for a motion compensated frame rate converter including a global affine motion estimation engine, a global translation motion estimation engine, a segmentation mask generator, an object edge strength map generator and a local motion estimation engine. Combinations of these features are implemented in a motion compensated picture rate converter to accurately and efficiently provide motion estimation and compensation for a sequence of frames.

Abstract: The invention includes a system and the associated method for reducing memory access bandwidth in various sections of one or more video pipeline stages of one or more channels in order to produce multiple high quality video signals. Signal processing stages of a video processor may share portions of memory on and off chip to reduce memory access bandwidth. A blank time optimizer may receive a memory access request at a first clock rate and access the memory using a second clock rate which may be slower than the first to provide more bandwidth for another memory access request at the same or a later time. Video signals may be scaled relative to various memory access points to further reduce memory storage requirements. A color management unit may also be shared among one or more video signals by receiving combined video signals and identification information associated with each signal portion.

Abstract: A video noise reducer reduces the noise artifacts in a video signal. The video noise reducer is reconfigurable to provide spatial noise reduction and temporal noise reduction in either a parallel or cascade architecture. The video noise reducer is self-calibrating by providing estimation modules that estimate the amount of noise in the video signal and a noise injector that confirms the measurement against a known quantity of noise. The video noise reducer is adaptive to solutions in hardware or a combination of hardware and firmware. The video noise reducer is also optimized for efficient memory usage in interlaced video signal processing applications.

Abstract: High-frequency noise is generated that approximates the appearance of traditional “film grain” for a digital video signal. By adding a relatively small amount of film grain noise, the video can be made to look more natural and more pleasing to the human viewer. The digital film grain generation can be used to mask unnatural smooth artifacts in digital video such as “blockiness” and “contouring” in the case of compressed video and/or used to provide visual enhancements or special effects to any digital video stream. The digital film grain generator can control grain size and the amount of film grain to be added.

Abstract: A video deinterlacing system receives interlaced video data at a non-deterministic rate and generates non-interlaced data as a function of the interlaced video data. The system includes processing units, some of which require clocking rates that differ from clocking rates required by other processing units. A timing generator responds to a base clock and to a data valid signal, that indicates arrival of a portion of the interlaced video data, to cause generation of a plurality of enable signals. Each of the enable signals operate to enable a corresponding one of the clocking rates required by the processing units. Video capture can be performed by causing capture of video frames that meet or exceed a specified quality level. The quality of the captured, still image, video can be improved by disabling certain enhancement functions performed to improve moving video images.

Abstract: A video deinterlacing system receives interlaced video data at a non-deterministic rate and generates non-interlaced data as a function of the interlaced video data. The system includes processing units, some of which require clocking rates that differ from clocking rates required by other processing units. A timing generator responds to a base clock and to a data valid signal, that indicates arrival of a portion of the interlaced video data, to cause generation of a plurality of enable signals. Each of the enable signals operate to enable a corresponding one of the clocking rates required by the processing units. Video capture can be performed by causing capture of video frames that meet or exceed a specified quality level. The quality of the captured, still image, video can be improved by disabling certain enhancement functions performed to improve moving video images.

Abstract: A digital address filter is provided which converts straight-line and arc analog stroke data into digitized images which comply with Bresenham raster display criteria and can be displayed on a raster scanned monitor or LCD. Data collected over a preselected (M pixel.times.M pixel) spatial window are repetitively matched against a set of pixel template patterns permitted by the Bresenham criteria. After each full-frame iteration, the display pixel(s) corresponding to the best-fit templates are lighted.

Abstract: The present invention is directed to an apparatus and method for converting a noncausal, two dimensional signal representative of a digitized image into an equivalent data format that can be filtered by recursive filters. The first step is to estimate an optimal set of parameters by: generating data representative of a potential matrix which represents the signal for a given set of parameters; filtering the potential matrix to arrive at a statistically equivalent recursive data format; inputting white noise to the recursive data format to generate k samples of the signal; obtaining an average value for the correlation {.chi..sub..tau. }; generating data representative of a gradient of a likelihood function; using that data to minimize the likelihood function; comparing the arrived at set of parameters to a previously arrived at set of parameters to determine whether the difference therebetween is within a desired tolerance; and repeating the previous steps until an optimal set of parameters is estimated.