Abstract: An improved ECL circuit in which reference voltages have been eliminated is provided. The base of the reference switching transistor which is usually connected to a reference voltage is instead connected to the emitter of an emitter follower transistor coupled to the input switching transistor. The need for a reference voltage is thus eliminated because the emitter of such emitter follower transistor, and thus the base of the reference switching transistor, will be at the opposite level of the input to the base of the input switching transistor.

Abstract: A combination circuit formed of a functional portion circuit coupled to a latch or flip-flop circuit portion which is fabricated as a single gate on an integrated circuit semiconductor chip. The functional circuit portion can be a multiplexer, or other logic functions such as AND, NAND, OR, NOR, XOR, etc. A special buffer circuit is provided which generates a latch enable signal for the latch or a clock signal for the flip-flop in the combination circuit. The latch enable signal or the clock signal for the combination circuit has to override the high level values of the normal second level ECL signals while their low level values can be the same as those of normal second level ECL signals. This combination circuit has the advantage of higher speed, lower power consumption, and reduced component counts which is favorable for integrated circuits.

Abstract: An improved ECL gate having faster output transition times without requiring additional current is provided. Two switching transistors have their emitter terminals connected to a first current source. A reference switching transistor has its base connected to a reference voltage and an input switching transistor has its base connected to an input terminal. An emitter follower transistor is coupled to each switching transistor. A second current source is connected to each of the emitter follower transistors by coupling circuitry which shunts current from one emitter follower to the other thereby increasing the transition speed of the outputs. In the preferred embodiment, the emitters of the current source transistors for the two outputs are coupled through a common resistance to ground. The collector of the inverting emitter-coupled transistor is coupled via a capacitor to the base of the current source transistor for the non-inverting output.

Abstract: An improved logic level translator circuit for translating logic signals of non-TTL circuits to logic signals of TTL circuits is presented. The translator circuit as presented includes circuitry for providing elimination of noise spiking and the resultant erroneous switching caused by simultaneous conduction of TTL circuit outputs as they change states.

Abstract: A unitary multiplexer-decoder circuit integrated on a single semiconductor chip includes a first reference transistor, a plurality of first data input transistors, a second reference transistor, a plurality of second data input transistors, an emitter follower, a first current source and a second current source. A reference voltage generator is provided for generating first and second reference potentials and is formed on the same integrated circuit substrate as the multiplexer-decoder circuit.