Abstract: A method and system for mitigating the impact of voltage supply variations on logic built-in self-test (LBIST) results. The method includes, but is not limited to: creating a set of customized LBIST activation patterns during IC design; propagating the activation patterns from the scan-able latches through the non-scan latches to the device under test; propagating the data from the device under test through the non-scan latches to the scan-able latches; capturing the data in a scan-able latch; and performing each test cycle independently such that the impact of voltage supply variations between test cycles is eliminated.