Abstract: Clock stations in a hybrid tree-mesh clock distribution network are placed and routed using placement information embedded in instance names of the macrocells that form the clock-distribution network. The instance name includes (X,Y) coordinate information corresponding to placement of the macrocell in the physical layout of the network design. Base cells in each macrocell are placed in a known deterministic arrangement, such as one on top of another in a layout of the clock distribution network, all at the same (X,Y) offset. Preferably, the base cells are all from a standard-cell library, thereby reducing design cost and debug.

Abstract: An electronic device fabrication tool uses only standard-size cells from a cell library to fabricate a clock distribution network on a semiconductor device, thereby reducing the cost of the fabrication process. Target clock drive strengths are determined to reduce skew along the clock-distribution network, and the standard size cells are combined to produce clock-driving components substantially equal to the target clock drive strengths. The cells are combined using VIA programming, by electrically coupling them by adding or removing vias connecting the cells. In hybrid tree-mesh clock distribution networks, VIA programming ensures that the binary tree portions of the network are not affected by the tuning. Preferably, the clock-driving elements are clock inverters or buffers, though other elements are able to be used to drive clock signals on the clock distribution network.

Abstract: Clock networks constructed with variable drive strength clock drivers are prepared for tuning. The clock drivers are built from a smaller set of base standard cells. Locations of the input and output netlists of the macrocells are marked and reserved even through the extraction process. The macrocells are able to be flattened, generating a netlist with the base cells, and recombined during circuit simulation, thereby reducing the number of iterations, making the tuning flow more efficient. The clock network is initially tuned by adding or removing cross-links in the mesh to balance capacitive loads on each driver of the clock mesh.

Abstract: According to one aspect of the present disclosure, a circuit includes a semiconductor device including a plurality of logic blocks and a plurality of programmable interconnects. A delay detector generates a delay signal responsive to a measured delay of an output signal, wherein the output signal is from at least one of the plurality of logic blocks. A biasing circuit responsive to the delay signal to adjust subsequent measured delays toward a predetermined value.

Abstract: According to one aspect of the present disclosure, a circuit includes a semiconductor device including a plurality of logic blocks and a plurality of programmable interconnects. A delay detector generates a delay signal responsive to a measured delay of an output signal, wherein the output signal is from at least one of the plurality of logic blocks. A biasing circuit responsive to the delay signal to adjust subsequent measured delays toward a predetermined value.