Abstract: A memory device includes a memory array comprising a plurality of memory cells. At least one of the memory cells comprises a pair of cross-coupled inverters, and a plurality of ports, including at least one write port. A given write port comprises at least one drive control circuit having an output coupled to respective gate terminals of both a write assist transistor and a drive transistor, with the write assist transistor being arranged in series with one of a pull-up and a pull-down path of a corresponding one of the inverters, and the drive transistor being configured to hold one of the internal nodes at a designated logic level in conjunction with a write operation. First and second drive control circuits of this type may generate complementary control signals for application to respective pairs of write assist and drive transistors associated with respective ones of the inverters.

Abstract: A memory device includes a memory array comprising a plurality of memory cells. At least one of the memory cells comprises a pair of cross-coupled inverters, and a plurality of ports, including at least one write port. A given write port comprises at least one drive control circuit having an output coupled to respective gate terminals of both a write assist transistor and a drive transistor, with the write assist transistor being arranged in series with one of a pull-up and a pull-down path of a corresponding one of the inverters, and the drive transistor being configured to hold one of the internal nodes at a designated logic level in conjunction with a write operation. First and second drive control circuits of this type may generate complementary control signals for application to respective pairs of write assist and drive transistors associated with respective ones of the inverters.

Abstract: An integrated circuit having a CAM array includes a plurality of CAM cells organized in rows and columns where each row corresponds to an address word and each column corresponds to a bit position, and a match line for each row connected to be shared by CAM cells in that row. The CAM array also includes a feedback circuit for each row connected to limit a discharge voltage for a corresponding match line in that row. In another aspect, a method of operating an integrated circuit having a CAM array includes organizing a plurality of CAM cells in rows and columns where each row corresponds to an address word and each column corresponds to a bit position, and sharing a match line with CAM cells in each row. The method also includes limiting a discharge voltage for the match line.

Abstract: Static random access memory (SRAM) cells are disclosed. In one example embodiment the SRAM cell includes a latch having a first node and a second node for storing bit information at the first node and a complement of the bit at the second node. The SRAM cell further includes a first switch controlled by a write operation signal, connected between a supply voltage and a first pull-up transistor of the latch and a third switch controlled the write operation signal, connected between the second node and a ground voltage. The SRAM cell further includes a second switch controlled by the write operation signal, connected between the supply voltage and a second pull-up transistor and a fourth switch controlled by the write operation signal, connected between the second node and the ground voltage. The write operation signals are generated by a first complex gate and a second complex gate.

Abstract: An integrated circuit having a CAM array includes a plurality of CAM cells organized in rows and columns where each row corresponds to an address word and each column corresponds to a bit position, and a match line for each row connected to be shared by CAM cells in that row. The CAM array also includes a feedback circuit for each row connected to limit a discharge voltage for a corresponding match line in that row. In another aspect, a method of operating an integrated circuit having a CAM array includes organizing a plurality of CAM cells in rows and columns where each row corresponds to an address word and each column corresponds to a bit position, and sharing a match line with CAM cells in each row. The method also includes limiting a discharge voltage for the match line.

Abstract: Static random access memory (SRAM) cells are disclosed. In one example embodiment the SRAM cell includes a latch having a first node and a second node for storing bit information at the first node and a complement of the bit at the second node. The SRAM cell further includes a first switch controlled by a write operation signal, connected between a supply voltage and a first pull-up transistor of the latch and a third switch controlled the write operation signal, connected between the second node and a ground. The SRAM cell further includes a second switch controlled by the write operation signal, connected between the supply voltage and a second pull-up transistor and a fourth switch controlled by the write operation signal, connected between the second node and the ground. The write operation signals are generated by a first complex gate and a second complex gate.