Patents by Inventor Nikhil Puri
Nikhil Puri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240144997Abstract: A semiconductor device includes a first memory array, a first bit line, a second memory array, a second bit line, a first conductive line and a first control circuit. The first bit line crosses over and is coupled to the first memory array, and extends along a first direction. The second bit line crosses over the second memory array, and is coupled to the first bit line. The first conductive line crosses over the second memory array and a part of the first memory array, and is configured to operate as a part of a first capacitor. The first control circuit is configured to couple the first conductive line to the second bit line when the first memory array is written.Type: ApplicationFiled: March 24, 2023Publication date: May 2, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Venkateswara Reddy KONUDULA, Teja MASINA, Nikhil PURI, Yen-Huei CHEN, Hung-Jen LIAO
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Publication number: 20240079052Abstract: A semiconductor device includes a first memory bank, a second memory bank and a first write driver. The first memory bank is coupled to a plurality of first data lines, and configured to operate according to a first data signal. The second memory bank is configured to operate according to the first data signal. The first write driver is disposed between the first memory bank and the second memory bank, and configured to adjust a voltage level of one of the plurality of first data lines when the first memory bank is written according to the first data signal.Type: ApplicationFiled: March 24, 2023Publication date: March 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Nikhil PURI, Venkateswara Reddy KONUDULA, Teja MASINA, Yen-Huei CHEN, Hung-Jen LIAO, Hidehiro FUJIWARA
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Publication number: 20230395160Abstract: A memory circuit includes first and second memory segments coupled to first and second write lines, and first and second write line circuits coupled to the first and second write lines and configured to receive first and second data signals. The first and second data signals have complementary low and high logical states during a write operation to the first or second memory segment, and each of the first and second data signals has the low logical state during a masked write operation to the first or second memory segment. The first and second write line circuits output, to the first and second write lines, first and second write line signals responsive to the first and second data signals during the write operation and float the first and second data lines during the masked write operation.Type: ApplicationFiled: July 31, 2023Publication date: December 7, 2023Inventors: Manish ARORA, Yen-Huei CHEN, Hung-Jen LIAO, Nikhil PURI, Yu-Hao HSU
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Patent number: 11798632Abstract: A write line circuit includes a power supply node configured to carry a power supply voltage level, a reference node configured to carry a reference voltage level, an output node, first and second switching devices coupled in series between the output node and the power supply node, and a third switching device directly coupled to each of the output node and the reference node. The first switching device is configured to selectively couple the output node to the second switching device responsive to a first data signal, the second switching device is configured to selectively couple the first switching device to the power supply node responsive to a second data signal, and the third switching device is configured to selectively couple the output node to the reference node responsive to the first data signal.Type: GrantFiled: May 6, 2021Date of Patent: October 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Manish Arora, Yen-Huei Chen, Hung-Jen Liao, Nikhil Puri, Yu-Hao Hsu
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Publication number: 20220019046Abstract: The present disclosure provides a thermal resistant water blocking tape for use in an optical fiber cable. The thermal resistant water blocking tape includes a water blocking tape. The water blocking tape is resistant to water penetration. The water blocking tape is defined by a top surface and a bottom surface. In addition, the water blocking tape has an intumescent material that reduces transmission of thermal radiations across the thermal resistant water blocking tape at elevated temperature. The intumescent material may be coated on the water blocking tape. The intumescent material may produce insulating carbonaceous foam at elevated temperature.Type: ApplicationFiled: March 27, 2021Publication date: January 20, 2022Inventors: Pramod Marru, Vikash Shukla, Atulkumar Mishra, Nikhil Puri, Santhosh Ghorpade
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Publication number: 20210257029Abstract: A write line circuit includes a power supply node configured to carry a power supply voltage level, a reference node configured to carry a reference voltage level, an output node, first and second switching devices coupled in series between the output node and the power supply node, and a third switching device directly coupled to each of the output node and the reference node. The first switching device is configured to selectively couple the output node to the second switching device responsive to a first data signal, the second switching device is configured to selectively couple the first switching device to the power supply node responsive to a second data signal, and the third switching device is configured to selectively couple the output node to the reference node responsive to the first data signal.Type: ApplicationFiled: May 6, 2021Publication date: August 19, 2021Inventors: Manish ARORA, Yen-Huei CHEN, Hung-Jen LIAO, Nikhil PURI, Yu-Hao HSU
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Patent number: 11011238Abstract: A write line circuit includes a power supply node configured to carry a power supply voltage level, a reference node configured to carry a reference voltage level, a first input node configured to receive a first data signal, a second input node configured to receive a second data signal, a third input node configured to receive a control signal, and an output node. The write line circuit is configured to, responsive to the first data signal, the second data signal, and the control signal, either output one of the power supply voltage level or the reference voltage level on the output node, or float the output node.Type: GrantFiled: November 29, 2018Date of Patent: May 18, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Manish Arora, Hung-Jen Liao, Yen-Huei Chen, Nikhil Puri, Yu-Hao Hsu
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Publication number: 20200005877Abstract: A write line circuit includes a power supply node configured to carry a power supply voltage level, a reference node configured to carry a reference voltage level, a first input node configured to receive a first data signal, a second input node configured to receive a second data signal, a third input node configured to receive a control signal, and an output node. The write line circuit is configured to, responsive to the first data signal, the second data signal, and the control signal, either output one of the power supply voltage level or the reference voltage level on the output node, or float the output node.Type: ApplicationFiled: November 29, 2018Publication date: January 2, 2020Inventors: Manish ARORA, Hung-Jen LIAO, Yen-Huei CHEN, Nikhil PURI, Yu-Hao HSU
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Patent number: 10522214Abstract: A reliability aware negative bit-line write assist (RA-NBL) circuit comprises a coupling capacitor to provide a negative bump for write assist, and a control input generator control charging of the coupling capacitor, such that the negative bump is high at a low voltage, and the negative bump is low at a high voltage.Type: GrantFiled: June 8, 2017Date of Patent: December 31, 2019Assignee: Synopsys, Inc.Inventors: Sudhir Kumar, Vinay Kumar, Sumit Srivastava, Nikhil Puri
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Publication number: 20170358345Abstract: A reliability aware negative bit-line write assist (RA-NBL) circuit comprises a coupling capacitor to provide a negative bump for write assist, and a control input generator control charging of the coupling capacitor, such that the negative bump is high at a low voltage, and the negative bump is low at a high voltage.Type: ApplicationFiled: June 8, 2017Publication date: December 14, 2017Applicant: Synopsys, Inc.Inventors: Sudhir Kumar, Vinay Kumar, Sumit Srivastava, Nikhil Puri