Abstract: A method and apparatus for repairing a memory is provided. At least one memory is tested using a production test pattern. After the production test, a passing or failing status is determined for each memory tested. This determination may be made using a built-in repair analysis (BIRA) program. After the analysis the location of each failing memory is determined. A fuse register pattern is then determined for the failing memory, and at least one fuse is blown to repair the failed memory. The repair utilizes at least one of the redundant memories present in the semiconductor device. The apparatus includes a semiconductor device having repairable memories, a fuse programmable read-only memory (FPROM) that contains multiple redundant memories, and a fuse box memory repair apparatus that is in communication with the FRPOM and the multiple repairable memories.

Abstract: A method and apparatus for dynamic memory mode testing is provided. The method begins when an electronic device is reset before testing begins. A BIST mode is selected and then input to a BIST apparatus. The BIST mode is then performed and test results recorded. An additional BIST mode is then selected and testing using the additional BIST mode begins immediately. The apparatus includes a clock divider, a BIST controller in communication with the clock divider; a dynamic memory test module in communication with the clock divider, BIST controller and memory; and a low voltage test access port in communication with the BIST controller for receiving test output data from the BIST controller. The dynamic memory test module comprises: at least two AND gates in communication with at least three multiplexers.

Abstract: A method and apparatus for repairing a memory is provided. At least one memory is tested using a production test pattern. After the production test, a passing or failing status is determined for each memory tested. This determination may be made using a built-in repair analysis (BIRA) program. After the analysis the location of each failing memory is determined. A fuse register pattern is then determined for the failing memory, and at least one fuse is blown to repair the failed memory. The repair utilizes at least one of the redundant memories present in the semiconductor device. The apparatus includes a semiconductor device having repairable memories, a fuse programmable read-only memory (FPROM) that contains multiple redundant memories, and a fuse box memory repair apparatus that is in communication with the FRPOM and the multiple repairable memories.

Abstract: Embodiments contained in the disclosure provide a method for memory built-in self-testing (MBIST). The method begins when a testing program is loaded, which may be from an MBIST controller. Once the testing program is loaded MBIST testing begins. During testing, memory failures are determined and written to a failure indicator register. The writing to the failure indicator register occurs in parallel with the ongoing MBIST testing. An apparatus is also provided. The apparatus includes a memory data read/write block, a memory register, a memory addressor, and a memory read/write controller. The apparatus communicates with the memories under test through a memory address and data bus.

Abstract: Embodiments contained in the disclosure provide a method for memory built-in self-testing (MBIST). The method begins when a testing program is loaded, which may be from an MBIST controller. Once the testing program is loaded MBIST testing begins. During testing, memory failures are determined and written to a failure indicator register. The writing to the failure indicator register occurs in parallel with the ongoing MBIST testing. An apparatus is also provided. The apparatus includes a memory data read/write block, a memory register, a memory addressor, and a memory read/write controller. The apparatus communicates with the memories under test through a memory address and data bus.

Abstract: A method and apparatus for testing secure blocks is provided. The method begins when instructions for testing a secure memory are loaded using a parallel testing interface. Instructions for testing the non-secure memory may be resident on the device as Built-In-Self-Test (BIST) instructions. In that case, the instructions are then accessed through the standard test access. Testing occurs simultaneously for the secure memory and the non-secure memory using both the parallel interface and the standard test interface. Testing both the secure memory blocks and the non-secure memory blocks using the parallel and standard test interfaces saves time during the test process.